Mario1159/verilator
1
0
Fork 0
forked from github/verilator
Code Pull Requests Releases 1 Activity
5,500 Commits 9 Branches 150 Tags 43 MiB
196f3292d5
Commit Graph

5500 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
HungMingWu
196f3292d5 Improve V3Ast function usage ergonomics (#3650) 
Signed-off-by: HungMingWu <u9089000@gmail.com>
 2022-10-21 14:12:12 +01:00
Arkadiusz Kozdra
627a144b83
Support access to constructs inside type parameters (#3702) 
This changeset brings support for accesses like:

	class Cls#(type TYPE1);
	    TYPE1::some_method();
	endclass

It is done by delaying dot resolution on type parameters until they get
resolved by V3Param, and doing a more thorough reference skip.
 2022-10-21 09:00:40 -04:00
Krzysztof Bieganski
5688d1a935
Internals: Add V3UniqueNames consistency assertion (#3692) 2022-10-21 07:05:38 -04:00
Geza Lore
8b0d71994d DFG: don't try to call DfgVertex::width() on arrays 
In DFG DfgVertex::width() is only defined for vertices representing
packed values, which DfgVertex::hash() used to violate. The only
non-packed values at the moment are DfgVarArray, which is a
DfgVertexVar, which are handled specially anyway, so this is easy to
fix.

Fixes #3682
 2022-10-21 10:57:13 +01:00
Wilson Snyder
79682e6072 Support empty generate_regions (#3695). [mpb27] 2022-10-20 22:04:50 -04:00
Wilson Snyder
7e1b92fa75 Add --get-supported to determine what features are in Verilator (#3688). 2022-10-20 21:42:30 -04:00
Wilson Snyder
ca8ef7ce73 github: upload-artifacts/download-artifacts/cache@v3 (#3700) 2022-10-20 20:23:04 -04:00
Wilson Snyder
23d538fdaf github: upload-artifacts/download-artifacts/cache@v3 2022-10-20 20:04:45 -04:00
Wilson Snyder
aaadc3def7 github: Use checkout@v3 (#3700) 2022-10-20 19:57:50 -04:00
Krzysztof Bieganski
444a4a760c
Support timing with more Clang and libc++ versions (#3669) (#3698) 2022-10-20 19:54:22 -04:00
Wilson Snyder
b42799f3b5 Commentary 2022-10-20 19:48:13 -04:00
Geza Lore
7b07cf912e Delete trigger dump when --protect-ids is used 
In order to not leak signal names with --protect-ids, we simply make the
trigger dump function empty (this is a debug only construct).

Partial fix for #3689
 2022-10-20 15:44:51 +01:00
Geza Lore
6a3ec17887 DFG: Do not inline SystemC variables 
The emitted SystemC types (e.g. sc_bv) are not interchangeable with
Verilator internal C++ types (e.g.: VlWide), so the variables themselves
are not interchangeable (but can be assigned to/from each other). We can
preserve correctness simply be not inlining any SystemC variables (i.e.:
don't simplify any 'sc = nonSc' or 'nonSc = sc' assignments). SystemC
types only appear at top level ports so this should have no significant
impact.

Fixes #3688
 2022-10-20 15:44:51 +01:00
Krzysztof Bieganski
8c3ca30c91
Fix print format warning on some platforms (#3699) 2022-10-20 10:15:29 -04:00
Arkadiusz Kozdra
0e4da3b0bf
Support virtual interfaces (#3654) 2022-10-20 06:31:00 -04:00
Krzysztof Bieganski
e6add5e0b8
Fix trace activity with --timing (#3576) (#3678) (#3696) 2022-10-20 06:28:55 -04:00
Krzysztof Bieganski
22243d1e49
Support class type params without defaults (#3693) 2022-10-19 21:59:26 -04:00
Krzysztof Bieganski
bec0b7d4d0
Disallow delays with --lib-create (#3691) 2022-10-19 20:52:29 -04:00
Wilson Snyder
f6f13c7fda Internals: Comment out debug that may flag ASAN problem (#3574) 2022-10-18 21:17:52 -04:00
Wilson Snyder
e7068369fe Fix $display of fixed-width numbers (#3565). 2022-10-18 21:10:35 -04:00
Wilson Snyder
b930d0731a Fix foreach and pre/post increment in functions (#3613). 2022-10-18 20:04:09 -04:00
Wilson Snyder
2723223884 Fix LSB error on --hierarchical submodules (#3539). 2022-10-18 17:29:51 -04:00
Kamil Rakoczy
b6c116d4bf
Internals: Add VL_MT_SAFE annotations to const functions (#3681) 2022-10-18 17:07:09 -04:00
Kamil Rakoczy
54e3f15dce
Internals: Add attribute when using clang to VL_MT_SAFE and VL_MT_UNSAFE (#3685) 2022-10-18 05:15:33 -04:00
github action
c057847760 Apply 'make format' 2022-10-17 23:52:01 +00:00
Topa Topino
46c5764383
Split UNUSED warning into genvar, param, and signal warnings (#3607) 2022-10-17 19:51:13 -04:00
Wilson Snyder
22ce36012e Add VERILATOR_TIMING define (#3684) 2022-10-17 18:18:56 -04:00
Geza Lore
5c65e0cfa1 Dfg: Fix incorrect folding of associative expressions with shared terms 
Fixes #3679
 2022-10-17 15:03:30 +01:00
Geza Lore
840e26b69a Fix incorrect return in DFG decomposition 
Fixes #3676
 2022-10-17 14:41:20 +01:00
Krzysztof Bieganski
5e79652922
Test tracing with --timing and --main (#3656) 
Add a test for tracing with `--main` and `--timing`.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-10-17 12:36:37 +02:00
Wilson Snyder
cb7b024e8f Commentary: Spelling, and add upgrade notes (#3462) 2022-10-16 11:10:41 -04:00
Wilson Snyder
f3292a3651 Tests: Prove fixed (#2410) 2022-10-16 10:36:18 -04:00
Wilson Snyder
76ccd332a6 Internals: Remove DETECTARRAY, dead code. 2022-10-16 09:41:51 -04:00
Wilson Snyder
3cd2c8532d Internals: Cleanup spacing of Vi for loops. 2022-10-15 18:47:10 -04:00
Wilson Snyder
c0739e908c Fix internal traceActivity to be zero reset not randomized. 2022-10-15 18:37:44 -04:00
Wilson Snyder
379a947379 Tests: Fix some internal code coverage holes 2022-10-15 13:59:07 -04:00
Wilson Snyder
916a3d9066 Fix --main --trace missing initial timestep (#3678). 2022-10-15 13:24:38 -04:00
Wilson Snyder
b16b607b98 Commentary: Changes update 2022-10-15 11:04:03 -04:00
Wilson Snyder
732d5bea10 Commentary: Standard format for company contributions 2022-10-15 10:59:31 -04:00
Wilson Snyder
d9a0d0ade2 Commentary (fix earlier commit) 2022-10-15 10:57:46 -04:00
Wilson Snyder
e32ff0e1a6 Tests: Better mailbox and semaphore tests. 2022-10-15 10:37:24 -04:00
Wilson Snyder
5957156dee Tests: Fix bad result check. 2022-10-15 06:57:12 -04:00
Wilson Snyder
14f58ed6c7 Add error on real edge event control. 2022-10-15 06:21:34 -04:00
Arkadiusz Kozdra
038d57070b
Support standalone 'this' in classes (#3675) (#2594) (#3248) 2022-10-14 08:55:55 -04:00
Krzysztof Bieganski
8a347248f5
Use AstDelay nodes for intra-assignment delays (#3672) 
Also fix messy implementation of net delays.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-10-14 09:35:26 +02:00
Krzysztof Bieganski
caed086516
Move Postponed logic after the eval loop (#3673) 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-10-13 21:04:43 +02:00
Krzysztof Bieganski
68927d4fd3
Make class ref typing stricter (#3671) 
Prevents the possibility of assigning an integer to a class reference,
both at the SystemVerilog and the emitted C++ levels.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-10-13 14:33:15 +02:00
Geza Lore
b2070a9407 Commentary: Mention DFG in changes 2022-10-12 10:21:02 +01:00
github action
8dacbdec3a Apply 'make format' 2022-10-11 09:04:38 +00:00
Geza Lore
2a110c91cf Speed up DfgGraph decomposition algorithms 2022-10-11 09:55:08 +01:00