Test tracing with --timing and --main (#3656)

Add a test for tracing with `--main` and `--timing`.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>

test_regress/t/t_timing_clkgen1.v

@@ -4,6 +4,8 @@
 // any use, without warranty, 2020 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+`define STRINGIFY(x) `"x`"
+
 module clkgen(output bit clk);
    initial begin
       #(8.0:5:3) clk = 1;  // Middle is default
@@ -38,4 +40,11 @@ module t(/*AUTOARG*/);
          $finish;
       end
    end
+
+`ifdef TEST_TRACING
+   initial begin
+     $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+     $dumpvars;
+   end
+`endif
 endmodule

test_regress/t/t_timing_clkgen_unsup.out

@@ -1,5 +1,5 @@
-%Warning-MINTYPMAXDLY: t/t_timing_clkgen1.v:9:13: Unsupported: minimum/typical/maximum delay expressions. Using the typical delay
-    9 |       #(8.0:5:3) clk = 1;   
+%Warning-MINTYPMAXDLY: t/t_timing_clkgen1.v:11:13: Unsupported: minimum/typical/maximum delay expressions. Using the typical delay
+   11 |       #(8.0:5:3) clk = 1;   
       |             ^
                        ... For warning description see https://verilator.org/warn/MINTYPMAXDLY?v=latest
                        ... Use "/* verilator lint_off MINTYPMAXDLY */" and lint_on around source to disable this message.

test_regress/t/t_timing_trace.out

@@ -1,8 +1,8 @@
 $version Generated by VerilatedVcd $end
-$date Thu Aug 25 09:56:30 2022 $end
+$date Wed Oct  5 13:59:40 2022 $end
 $timescale 1ps $end
 
- $scope module top $end
+ $scope module TOP $end
   $scope module t $end
    $var wire  1 # clk $end
    $var wire 32 $ cyc [31:0] $end

test_regress/t/t_timing_trace.pl

@@ -17,8 +17,8 @@ else {
     top_filename("t/t_timing_clkgen1.v");
 
     compile(
-        verilator_flags2 => ["--timing --trace -Wno-MINTYPMAXDLY"],
-        timing_loop => 1
+        verilator_flags2 => ["--exe --main --timing --trace -Wno-MINTYPMAXDLY -DTEST_TRACING"],
+        make_main => 0,
         );
 
     execute(