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Support empty generate_regions (#3695). [mpb27]

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Wilson Snyder 2022-10-20 22:04:50 -04:00
parent 7e1b92fa75
commit 79682e6072
3 changed files with 11 additions and 0 deletions
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@ -34,6 +34,7 @@ Verilator 5.001 devel
* Support standalone 'this' in classes (#2594) (#3248) (#3675). [Arkadiusz Kozdra, Antmicro Ltd]
* Support tristate select/extend (#3604). [Ryszard Rozak, Antmicro Ltd>
* Support linting for top module interfaces (#3635). [Kanad Kanhere]
* Support empty generate_regions (#3695). [mpb27]
* Add --dump-tree-dot to enable dumping Ast Tree .dot files (#3636). [Marcel Chang]
* Add --get-supported to determine what features are in Verilator.
* Add error on real edge event control.

4
src/verilog.y
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@ -1645,6 +1645,8 @@ program_generate_item<nodep>: // ==IEEE: program_generate_item
loop_generate_construct { $$ = $1; }
| conditional_generate_construct { $$ = $1; }
| generate_region { $$ = $1; }
// not in IEEE, but presumed so can do yBEGIN ... yEND
| genItemBegin { $$ = $1; }
| elaboration_system_task { $$ = $1; }
;
@ -2424,6 +2426,8 @@ module_item<nodep>: // ==IEEE: module_item
non_port_module_item<nodep>: // ==IEEE: non_port_module_item
generate_region { $$ = $1; }
// not in IEEE, but presumed so can do yBEGIN ... yEND
| genItemBegin { $$ = $1; }
| module_or_generate_item { $$ = $1; }
| specify_block { $$ = $1; }
| specparam_declaration { $$ = $1; }

6
test_regress/t/t_gen_if.v
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@ -14,6 +14,12 @@ module t(data_i, data_o, single);
output [31:0] data_o;
input single;
// Bare begin/end extension of IEEE allowed by most all tools
begin
end
begin : named
end : named
//simplistic example, should choose 1st conditional generate and assign straight through
//the tool also compiles the special case and determines an error (replication value is 0
generate