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Commentary: Mention DFG in changes

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Geza Lore 2022-10-11 10:06:05 +01:00
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@ -19,6 +19,8 @@ Verilator 5.001 devel
clocks are now simulated correctly (#3278, #3384). [Geza Lore, Shunyao CAD]
* Support timing controls (delays, event controls in any location, wait
statements) and forks. See docs for details. [Krzysztof Bieganski, Antmicro Ltd]
* Introduce a new combinational logic optimizer (DFG), that can yield
significant performance improvements on some designs. [Geza Lore, Shunyao CAD]
* Add --binary option as alias of --main --exe --build --timing (#3625).