Add very basic support for vpiModule. Basically it allows to traverse
the module tree to find a variable etc. It does not support more than
vpi_iterate and vpi_scan for vpiModule along basic operations like
vpi_get_str on vpiModule.
The support is added non-intrusively to non-VPI verilator runs. It
essentially:
- Tracks the creation of cell instances and keeps them alive until
the emit phase. They are there converted to scopes if modules.
- Emits empty (don't add anything during construction)
VerilatedScopes for all inlined modules, only for those inlined
modules that are on the hierarchical path to public variables.
- Adds VerilatedHierarchy as abstraction to structure of the
scopes. It is only created for VPI designs. It allows to traverse
the hierarchy from the top (NULL).
Signed-off-by: Stefan Wallentowitz <stefan@wallentowitz.de>
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
This switch exposes VARs, PORTs and WIREs to C++ code. It must be use
with care as it has a significant performance impact and may result in
mis-simulation of generated clocks. Anyhow, it is prefered over
--public and useful for VPI.
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Stefan Wallentowitz <stefan@wallentowitz.de>
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
VerilatedVpi::callCbs() can be used by the user to signal
simulation-related callbacks, e.g.
VerilatedVpi::callCbs(cbStartOfSimulation).
The information if any callbacks have been called may be important to
drive an evaluation until no further changes are observed.
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Philipp Wagner <mail@philipp-wagner.com>
Signed-off-by: Stefan Wallentowitz <stefan@wallentowitz.de>
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
