Fix ugly error on interface misuse, bug1525.

Changes

@@ -20,6 +20,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix vpiType accessor, bug1509, bug1510. [Stefan Wallentowitz]
 
+****  Fix ugly error on interface misuse, bug1525. [Bogdan Vukobratovic]
+
 
 * Verilator 4.018 2019-08-29
 

src/V3Width.cpp

@@ -3520,6 +3520,12 @@ private:
                 // child node's width to end up correct for the assignment (etc)
                 widthCheckSized(nodep, side, underp, expDTypep, extendRule, warnOn);
             }
+            else if (!VN_IS(expDTypep, IfaceRefDType)
+                     && VN_IS(underp->dtypep(), IfaceRefDType)) {
+                underp->v3error(ucfirst(nodep->prettyOperatorName())
+                                <<" expected non-interface on "<<side
+                                <<" but '"<<underp->name()<<"' is an interface.");
+            }
             else {
                 // Hope it just works out
             }

test_regress/t/t_interface_asvar_bad.out

@@ -0,0 +1,9 @@
+%Error: t/t_interface_asvar_bad.v:28: Operator ASSIGN expected non-interface on Assign RHS but 'itf' is an interface.
+                                    : ... In instance t.source
+      getter = itf;   
+               ^~~
+%Error: t/t_interface_asvar_bad.v:29: Operator ADD expected non-interface on RHS but 'itf' is an interface.
+                                    : ... In instance t.source
+      getter = 4'd3 + itf;   
+                      ^~~
+%Error: Exiting due to

test_regress/t/t_interface_asvar_bad.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(linter => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_interface_asvar_bad.v

@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   counter_if iface();
+
+   source source (
+      .itf  (iface)
+   );
+
+endmodule
+
+interface counter_if;
+   logic [3:0] value;
+endinterface
+
+module source
+  (
+   counter_if itf
+   );
+
+   logic [3:0] getter;
+
+   initial begin
+      getter = itf;  // Intended to write itf.value
+      getter = 4'd3 + itf;  // Intended to write itf.value
+   end
+
+endmodule