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Fix bad module name.

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This commit is contained in:
Wilson Snyder 2019-09-16 21:09:18 -04:00
parent baa634343b
commit 3469c78153
1 changed files with 2 additions and 2 deletions
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4
test_regress/t/t_lint_implicit_port.v
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@ -12,12 +12,12 @@ module t (/*AUTOARG*/
logic oe;
read r (.clk(clk), .data( ( ( oe == 1'd001 ) && implicit_write ) ) );
set s (.clk(clk), .enable(implicit_write));
sets s (.clk(clk), .enable(implicit_write));
read u (.clk(clk), .data(~implicit_also));
endmodule
module set (
module sets (
input clk,
output enable
);