RVSCC/rtl/priority_encoder.sv

20 lines
418 B
Systemverilog
Raw Normal View History

`include "timescale.sv"
2023-01-01 22:28:56 +00:00
// 2**N to N Priority encoder
2023-02-26 23:26:11 +00:00
module priority_encoder #(
2023-01-29 04:55:22 +00:00
parameter int N = 4
) (
input logic [2**N - 1:0] data_in,
output logic [N - 1:0] data_out,
2023-01-01 22:28:56 +00:00
output logic valid
);
2023-01-29 04:55:22 +00:00
always_comb begin
2023-03-02 20:20:10 +00:00
data_out = N'('dx);
2023-01-29 04:55:22 +00:00
for (int i = 0; i < 2 ** N; i++) begin
2023-02-01 16:20:37 +00:00
if (data_in[i]) data_out = i[N-1:0];
2023-01-01 22:28:56 +00:00
end
2023-01-29 04:55:22 +00:00
if (data_in == 0) valid = 0;
else valid = 1;
end
2023-01-01 22:28:56 +00:00
endmodule