Linter corrections

rtl/ALU.sv

@@ -10,21 +10,15 @@ module ALU #(
     output logic [  3:0] status
 );
   logic n, z, c, v;
-  logic opsign_comp, v_value;
   always_comb begin
-    // Check if the signs of the operands are equal considering substraction sign simplification over the B operand
-    opsign_comp = (a[N-1] == (b[N-1] ^ opcode[0]));
-    // There is an overflow if the signs are equal and the result differ from the operation sign
-    // The overflow flag only gets assign when the operation is either a sum or a substraction
-    v_value = opsign_comp && (result != a[N-1]);
     case (opcode)
       'b000: begin  // Addition
         {c, result} = a + b;
-        v = v_value;
+        v = (result[N-1] & !a[N-1] & !b[N-1]) | (!result[N-1] & a[N-1] & b[N-1]);
       end
       'b001: begin  // Substraction
         {c, result} = a - b;
-        v = v_value;
+        v = (result[N-1] & !a[N-1] & !b[N-1]) | (!result[N-1] & a[N-1] & b[N-1]);
       end
       'b011: begin  // Or
         result = a | b;
@@ -37,14 +31,14 @@ module ALU #(
         v = 'b0;
       end
       'b101: begin  // Set less than
-        result = a < b;
+        result = {31'd0, a < b};
         c = 'b0;
         v = 'b0;
       end
       default: begin
         result = 'dx;
-        c = 'dx;
-        v = 'dx;
+        c = 1'bx;
+        v = 1'bx;
       end
     endcase
     n = result[N-1];

rtl/PriorityEncoder.sv

@@ -9,9 +9,9 @@ module PriorityEncoder #(
     output logic valid
 );
   always_comb begin
-    data_out = 'dx;
+    data_out = 3'dx;
     for (int i = 0; i < 2 ** N; i++) begin
-      if (data_in[i]) data_out = i;
+      if (data_in[i]) data_out = i[N-1:0];
     end
     if (data_in == 0) valid = 0;
     else valid = 1;

test/Test_ALU.sv

@@ -1,15 +1,25 @@
 `timescale 1ns / 1ps
 
-module Test_ALU();
-	logic[31:0] a, b;
-	logic[2:0] opcode;
-	logic[31:0] result;
-	logic[3:0] status;
-    ALU alu(a, b, opcode, result, status);
-    
-    initial begin
-        a = 'd3;
-        b = 'd11;
-        opcode = 'd0;
-    end
+module Test_ALU ();
+  logic [31:0] a, b;
+  logic [ 2:0] opcode;
+  logic [31:0] result;
+  logic [ 3:0] status;
+  ALU alu (
+      .a(a),
+      .b(b),
+      .opcode(opcode),
+      .result(result),
+      .status(status)
+  );
+
+  initial begin
+    a = 'd3;
+    b = 'd11;
+    opcode = 'd0;
+    assert(result != 'd14) $display("3 + 11 != 14");
+    assert(status != 'b0000) $display("status(3 + 11) != 0000");
+    $display("Test successful");
+    $finish;
+  end
 endmodule

test/Test_PriorityEncoder.sv

@@ -3,11 +3,16 @@
 module Test_PriorityEncoder();
     logic[7:0] data_in;
     logic[2:0] data_out;
-    PriorityEncoder#(.N(3)) encoder(data_in, data_out);
+    logic valid;
+    PriorityEncoder#(.N(3)) encoder(
+      .data_in(data_in),
+      .data_out(data_out),
+      .valid(valid)
+    );
     initial begin
         data_in = 'b00000001;
         for (int i = 0; i < 8; i++) begin
-            assert (data_out == i + 1) else $error("[One-hot] Failed at " + i);
+            assert (data_out == i[2:0] + 1 || valid == 1) else $error("[One-hot] Failed at %d", i);
             #1
             data_in = data_in << 'd1;
         end
@@ -17,5 +22,6 @@ module Test_PriorityEncoder();
         #1
         data_in = 'b10101010;
         assert (data_out == 'd7) else $error("[Manual entry] Failed at " + 7);
+        $finish;
     end
 endmodule