20 lines
418 B
Systemverilog
20 lines
418 B
Systemverilog
`include "timescale.sv"
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// 2**N to N Priority encoder
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module priority_encoder #(
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parameter int N = 4
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) (
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input logic [2**N - 1:0] data_in,
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output logic [N - 1:0] data_out,
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output logic valid
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);
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always_comb begin
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data_out = N'('dx);
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for (int i = 0; i < 2 ** N; i++) begin
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if (data_in[i]) data_out = i[N-1:0];
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end
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if (data_in == 0) valid = 0;
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else valid = 1;
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end
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endmodule
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