Fix cache memory test

rtl/cache_memory.sv

@@ -22,21 +22,21 @@ module cache_memory #(
   localparam int WaySize = $clog2(NUM_WAYS);
   localparam int SetSize = $clog2(NUM_SETS);
   localparam int TagSize = ADDR_SIZE - SetSize - ByteOffsetSize;
-  
+
   logic [NUM_WAYS - 1:0] hits;
   logic [WaySize-1:0] way;
   logic [WaySize-1:0] read_way;
-  priority_encoder #(.N(WaySize)) read_way_encoder (
+  priority_encoder #(
+      .N(WaySize)
+  ) read_way_encoder (
       .data_in(hits),
       .data_out(read_way),
       .valid(hit)
   );
-  
+
   always_comb begin
-    if(write_enable)
-        way = write_way;
-    else
-        way = read_way;
+    if (write_enable) way = write_way;
+    else way = read_way;
   end
 
   typedef struct packed {
@@ -66,7 +66,7 @@ module cache_memory #(
       ways[way][set].valid <= 1;
     end
   end
-  
+
   logic [NUM_WAYS - 1:0] valid_flags;
   always_comb begin
     for (int i = 0; i < NUM_WAYS; i++) begin
@@ -74,10 +74,12 @@ module cache_memory #(
       hits[i] = ways[i][set].valid && (tag == ways[i][set].tag);
     end
   end
-  
-  priority_encoder #(.N(WaySize)) populate_way_encoder (
-    .data_in(valid_flags),
-    .data_out(populate_way),
-    .valid('dz)
+
+  priority_encoder #(
+      .N(WaySize)
+  ) populate_way_encoder (
+      .data_in(valid_flags),
+      .data_out(populate_way),
+      .valid()
   );
 endmodule

rtl/priority_encoder.sv

@@ -9,7 +9,7 @@ module priority_encoder #(
     output logic valid
 );
   always_comb begin
-    data_out = 3'dx;
+    data_out = N'('dx);
     for (int i = 0; i < 2 ** N; i++) begin
       if (data_in[i]) data_out = i[N-1:0];
     end

test/CMakeLists.txt

@@ -101,5 +101,6 @@ rvscc_add_test(
 	NAME cache-memory
 	TOP test_cache_memory
 	SOURCES ${PROJECT_SOURCE_DIR}/rtl/cache_memory.sv
+  			${PROJECT_SOURCE_DIR}/rtl/priority_encoder.sv
 	        ${PROJECT_SOURCE_DIR}/test/test_cache_memory.sv
 )

test/test_cache_memory.sv

@@ -10,7 +10,7 @@ module test_cache_memory ();
   logic write_enable;
   logic [31:0] write_data;
   logic [31:0] read_data;
-  logic read_valid;
+  logic hit;
   logic [dut.WaySize-1:0] populate_way;
   cache_memory #(
       .ADDR_SIZE (32),
@@ -26,7 +26,7 @@ module test_cache_memory ();
       .write_enable(write_enable),
       .write_data(write_data),
       .read_data(read_data),
-      .read_valid(read_valid),
+      .hit(hit),
       .populate_way(populate_way)
   );
 
@@ -51,12 +51,12 @@ module test_cache_memory ();
     write_enable = 0;
     tag += 1;
     #1;
-    assert (read_valid == 0)
+    assert (hit == 0)
     else $error("Valid flags does not match");
     #ClockCycle;
     tag -= 1;
     #1;
-    assert (read_valid == 1)
+    assert (hit == 1)
     else $error("Valid flags does not match");
     $finish;
   end