23 lines
421 B
Systemverilog
23 lines
421 B
Systemverilog
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`timescale 1ns / 1ps
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// 2**N to N Priority encoder
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module PriorityEncoder #(
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parameter N = 4
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)(
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input logic[2**N - 1:0] data_in,
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output logic[N - 1:0] data_out,
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output logic valid
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);
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always_comb begin
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data_out = 'dx;
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for (int i = 0; i < 2**N; i++) begin
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if (data_in[i])
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data_out = i;
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end
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if (data_in == 0)
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valid = 0;
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else
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valid = 1;
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end
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endmodule
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