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Author SHA1 Message Date
Geza Lore
160f3ee4a7 Remove dead code, no functional change 2022-05-25 19:11:20 +01:00
Krzysztof Bieganski
3a310f19f0 Adjust loop conditions in VlTriggerVec functions 
This change is not a functional one; it is only meant to appease the
compiler with respect to warnings such as GCC's `-Wtype-limits`.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-25 18:45:59 +01:00
Krzysztof Bieganski
d7a75dc026 Merge branch 'master' into develop-v5 2022-05-25 11:06:38 +02:00
github action
a372e010bd Apply 'make format' 2022-05-25 04:51:51 +00:00
Wilson Snyder
530817191e Support non-ANSI interface port declarations (#3439). 2022-05-25 00:50:50 -04:00
Geza Lore
1282548a1c Only consider definitions in t_flag_csplit 2022-05-20 18:02:00 +01:00
Geza Lore
c7610ed044 Fix FST tracing thread in CMake build 2022-05-20 17:04:46 +01:00
Geza Lore
ffc1c51526 Commentary 2022-05-20 16:44:53 +01:00
Geza Lore
b130a8cfeb Add -DVM_TRACE_VCD in model builds with Make with --trace 2022-05-20 16:44:38 +01:00
Geza Lore
551bd284dd Rename some internals related to multi-threaded tracing 
Rename the implementation internals of current multi-threaded tracing to
be "offload mode". No functional change, nor user interface change
intended.
 2022-05-20 16:44:35 +01:00
Wilson Snyder
f0a2c98376 Commentary 2022-05-20 08:34:32 -04:00
Krzysztof Bieganski
9edccfdffa
Initial support for intra-assignment timing controls, net delays (#3427) 
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 19:19:44 +01:00
Geza Lore
1a056f6db9 Fix invalid conditional merging when starting at 'c = c ? a : b' 
Fixes #3409.
 2022-05-17 18:36:40 +01:00
Krzysztof Bieganski
e018eb7bac
Support AstClass::repairCache() after V3Class (#3431) 
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 09:22:43 -04:00
Krzysztof Bieganski
0a91ddf38a
Tests: Better grep check in t_foreach (#3435) 
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 09:20:59 -04:00
Krzysztof Bieganski
67bb2c640e
Tests: Rename t_timing_clkgen to t_timing_clkgen1 (#3430) 
This is a pre-PR to #3363, which will introduce more clock gen tests.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 09:19:51 -04:00
Krzysztof Bieganski
561eaa311d
Tests: Enable CI testing with GCC 10 (#3432) 
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 09:19:06 -04:00
Geza Lore
282887d9c6 Fix code coverage holes 
Fixes #3422
 2022-05-16 21:22:21 +01:00
Krzysztof Bieganski
3f7a248ed4
Refactor some of the Begin handling to a separate function (#3426) 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-16 20:45:33 +01:00
Krzysztof Bieganski
ecaa07a72a
Rename AstTimingControl to AstEventControl (#3425) 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-16 20:44:41 +01:00
Geza Lore
0e62cd11da Don't issue DEPRECATED for now no-op clock_enable attribute 
Fixes #3421
 2022-05-16 18:57:51 +01:00
Wilson Snyder
99bdc27be3 Internals: Cleanup some statics, trivial part towards (#3419) 2022-05-15 14:26:55 -04:00
Wilson Snyder
c3c46967dc Tests: Appease sanitizer (#3121). 2022-05-15 11:50:52 -04:00
Wilson Snyder
7f1a9239ab Commentary, fix typo (#3121) 2022-05-15 11:14:07 -04:00
Geza Lore
599d23697d
IEEE compliant scheduler (#3384) 
This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278
 2022-05-15 16:03:32 +01:00
Geza Lore
c8102c8ffe Fix typo 2022-05-15 16:01:35 +01:00
Wilson Snyder
5aa12e9b51 Add assert when VerilatedContext is mis-deleted (#3121). 2022-05-15 10:51:03 -04:00
Geza Lore
829437b20b Commentary - dependencies 2022-05-15 15:25:46 +01:00
Wilson Snyder
3c4131d45d Fix 'with' operator with type casting (#3387). 2022-05-15 09:53:48 -04:00
Wilson Snyder
ae8d8ee1ac Fix crash with misuse of display. 2022-05-15 09:29:45 -04:00
Geza Lore
39b7c47e7b Merge branch 'master' into develop-v5 2022-05-15 13:39:14 +01:00
Geza Lore
89ec3d16dc Allow const nodes in VNRef 
No functional change.
 2022-05-15 13:30:07 +01:00
Geza Lore
f6f03bc261 Merge branch 'master' into develop-v5 2022-05-15 12:05:12 +01:00
Wilson Snyder
7602c983c5 Commentary 2022-05-14 18:16:31 -04:00
HungMingWu
560efb2c9e
Internals: Fix memory leak in V3FileLine (#3407) (#3408). No functional change intended. 2022-05-14 18:15:38 -04:00
Wilson Snyder
c2328ef46a Spelling fixes. 2022-05-14 16:12:57 -04:00
Geza Lore
766fb56651 Merge branch 'master' into develop-v5 2022-05-14 10:30:45 +01:00
Wilson Snyder
f6035447ae Internals: Use mutable for mutexes. No functional change. 2022-05-13 07:21:39 -04:00
Wilson Snyder
38438b3373 Internals: Cleanup some defaults. No functional change. 2022-05-12 23:30:39 -04:00
Wilson Snyder
71dedccbbe Support compile time trace signal selection with tracing_on/off (#3323). 2022-05-12 22:28:08 -04:00
Martin Stadler
cddbe4642f
Fix cmake rules to support higher-level targest (#3377) (#3386). 
Don't add linker flags as generator expression to support linking `TARGET` to higher-level targets in a top-level CMakeLists.txt file.
 2022-05-11 21:33:05 -04:00
Wilson Snyder
bdfdc737a0 Internals: Cleanup V3Config. No functional change intended. 2022-05-11 00:47:52 -04:00
Wilson Snyder
3d045c3aee Internals: Cleanup some verilog.y formatting. No functional change. 2022-05-09 00:37:51 -04:00
HungMingWu
9583f152ee
Fix compile error when enable VL_LEAK_CHECKS (#3411). 
Signed-off-by: HungMingWu <u9089000@gmail.com>
 2022-05-08 20:49:13 -04:00
Wilson Snyder
5b2755d28d Untabify verilog.y (#3412). No functional change. 2022-05-08 20:46:18 -04:00
Geza Lore
bec4610e12 Merge branch 'master' into develop-v5 2022-05-08 15:50:50 +01:00
Kamil Rakoczy
9378259779
Fix UNOPTFLAT warning from initial static var (#3406) 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2022-05-06 10:24:03 +02:00
Wilson Snyder
3d762282b9 Fix hang with large case statement optimization (#3405). 2022-05-05 07:02:52 -04:00
Wilson Snyder
184ebe72a2 Merge branch 'master' into develop-v5 2022-05-02 22:27:58 -04:00
Wilson Snyder
30783e6a79 devel release 2022-05-02 22:23:05 -04:00