Mario1159/verilator
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8a5471e175
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508 Commits

Author SHA1 Message Date
Wilson Snyder
8a5471e175 Tests: skip test for bug462 2012-03-22 22:35:24 -04:00
Wilson Snyder
605fd9f8e1 Tests: Skip test for bug461 2012-03-22 22:15:35 -04:00
Wilson Snyder
2bda43875d Support += and -= in standard for loops, bug463. 2012-03-22 21:02:38 -04:00
Wilson Snyder
da0ecf59c6 Tests: Rename t_mem_packed_assign_bad since fails 2012-03-20 20:55:16 -04:00
Wilson Snyder
e5b1fdf668 Tests: Added additional SystemVerilog tests. 
Squashed commit of the following:

commit c1eeda7d472fc14a0ffd5c1712ae7f7c614073a1
Author: Iztok Jeras <iztok.jeras@gmail.com>
Date:   Tue Mar 20 16:39:44 2012 +0100

- fixed assignment operator in t_array_packed_write_read.v from = to <=
- added tests for enumerations (existing tests do not use methods like
next(), num(), ...)
- added t_sv_bus_mux_demux test, with packed arrays, structures and unions
 2012-03-20 19:28:35 -04:00
Wilson Snyder
204fb82975 Add very experimental --xml option 2012-03-20 16:13:10 -04:00
Wilson Snyder
c63b697636 Fix signed array warning, bug456. 2012-03-12 20:29:00 -04:00
Wilson Snyder
c0f7bc4b5e Tests: Parameter bug case 2012-03-09 19:35:37 -05:00
Wilson Snyder
7139c9ae59 Fix and document --gdb option, bug454. 2012-03-09 18:37:38 -05:00
Wilson Snyder
b73642f8a8 Report ENDLABEL on mismatching end labels, bug450. 2012-03-07 20:14:18 -05:00
Wilson Snyder
479b497528 Tests: Add new tests from Iztok Jeras, bug446, bug450. 2012-03-07 20:00:09 -05:00
Wilson Snyder
31b55d3844 Tests: Fix running different simulators simultaneously 2012-03-06 20:58:23 -05:00
Wilson Snyder
dbf4e08d09 Tests 2012-03-06 20:12:47 -05:00
Wilson Snyder
274359e6ee Tests: Bit extraction from non-logic types 2012-03-04 17:17:57 -05:00
Wilson Snyder
8687dcbce1 Internals: Add isRanged, more debug. No functional change. 2012-03-04 16:18:41 -05:00
Wilson Snyder
03dfbdb7b1 Fix inheriting signed type across untyped parameters. 2012-03-03 21:03:34 -05:00
Wilson Snyder
3c8519f245 Fix inheriting real type across untyped parameters. 2012-03-03 16:29:06 -05:00
Wilson Snyder
4d2cc3ebdd Tests: New param value test 2012-03-03 15:44:56 -05:00
Wilson Snyder
4637e06ad2 Fix backward widths in function output warning 2012-03-03 12:09:01 -05:00
Wilson Snyder
f4ca4edc64 Debug: Add default .gdbinit file 2012-03-02 20:59:47 -05:00
Wilson Snyder
f540362e36 Fix expansion of back-slashed escaped macros, bug441. 2012-02-25 21:31:36 -05:00
Wilson Snyder
09c10492ab Fix hang on recursive substitution `defines, bug443. 2012-02-23 21:54:37 -05:00
Wilson Snyder
c8e4b1fc84 Fix functions inside generate for block. 2012-02-21 22:23:06 -05:00
Wilson Snyder
0de7cece5b Fix hang when functions inside begin block. 2012-02-21 21:25:11 -05:00
Wilson Snyder
f1546abf09 Fix error when using UDPs without --bbox-unsup 2012-02-20 09:02:59 -05:00
Wilson Snyder
3083562f6f tests: Avoid massive make parallelism. 2012-02-17 21:40:52 -05:00
Wilson Snyder
f13ffe2098 Internals: Merge from VHDL branch. Minor stuff, no functional change. 2012-02-11 20:40:58 -05:00
Wilson Snyder
660bc757f1 Tests: Remove debug 2012-02-04 20:00:36 -05:00
Wilson Snyder
9df8966f4a Support arrayed SystemC I/O pins. 2012-02-01 20:20:43 -05:00
Wilson Snyder
af9e85bda1 Fix memory delayed assignments from multiple clock domains. 2012-01-26 08:10:50 -05:00
Wilson Snyder
35c53865fb Check c style array 2012-01-25 19:23:41 -05:00
Wilson Snyder
d17f812827 Fix BLKSEQ warnings on variables declared inside always. 2012-01-19 21:15:21 -05:00
Wilson Snyder
2396181bc5 Add SYSTEMC_INCLUDE and SYSTEMC_LIBDIR 2012-01-19 20:30:41 -05:00
Wilson Snyder
c2c7c7bd9a Copyright year update 2012-01-15 10:26:28 -05:00
Wilson Snyder
c4504a9221 tests: Fix t_dist_install breaking corunning test 2011-12-15 18:39:51 -05:00
Wilson Snyder
f6fab74436 tests: GHDL test driver support 2011-12-09 19:58:14 -05:00
Wilson Snyder
362d642c87 Support "generate for (genvar i=0; ...". 2011-11-29 18:23:18 -05:00
Wilson Snyder
e4c96d5be5 Fix array of instantiations with sub-range output, bug414. 2011-11-28 22:10:43 -05:00
Wilson Snyder
f488701adc Fix dpi exports with > 32 bit but < 64 bit args, bug423. 2011-11-28 21:15:57 -05:00
Wilson Snyder
8ff2bf51c5 Merge branch 'master' of ssh://git-verilator-wsnyder/git/verilator 2011-11-28 09:48:14 -05:00
Wilson Snyder
a2490a55a9 tests: Test $countones on other simulators 2011-11-28 09:48:01 -05:00
Wilson Snyder
20189f5191 Fix empty generate region, bug422. 2011-11-28 07:49:36 -05:00
Wilson Snyder
06b796c6bd Suppress VARHIDDEN on dpi import arguments. 2011-11-27 12:03:22 -05:00
Wilson Snyder
bedf946fb2 Support V-AMS wreal 2011-11-27 10:31:06 -05:00
Wilson Snyder
b9e67157c6 With "--language VAMS" support a touch of Verilog AMS. 2011-11-25 00:49:38 -05:00
Wilson Snyder
b30b2a183b Support . 2011-11-20 02:01:48 -05:00
Wilson Snyder
9ab3bcdde3 Support with %g. 2011-11-20 01:01:02 -05:00
Wilson Snyder
5df3bbe188 Fix $display with %d following %g. 2011-11-20 00:45:59 -05:00
Wilson Snyder
b7c2c83c88 Fix bad result with if-else-return optimization, bug420. 2011-11-12 08:07:30 -05:00
Wilson Snyder
88a2b0b911 Support constants in sensitivity lists, bug412. 2011-11-02 18:34:17 -04:00