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Internals: Add isRanged, more debug. No functional change.

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This commit is contained in:
Wilson Snyder 2012-03-04 16:18:41 -05:00
parent 03dfbdb7b1
commit 8687dcbce1
8 changed files with 35 additions and 18 deletions
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2
src/V3Ast.cpp
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@ -951,7 +951,7 @@ void AstNode::checkTree() {
void AstNode::dumpGdb() { // For GDB only
if (!this) { cout<<"This=NULL"<<endl; return; }
dumpGdbHeader();
dump(cout);
cout<<" "; dump(cout); cout<<endl;
}
void AstNode::dumpTreeGdb() { // For GDB only
if (!this) { cout<<"This=NULL"<<endl; return; }

22
src/V3AstNodes.cpp
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@ -496,17 +496,17 @@ void AstWhile::addNextStmt(AstNode* newp, AstNode* belowp) {
//======================================================================
// Per-type Debugging
void AstNode::dump(ostream& os) {
os<<typeName()<<" "<<(void*)this
void AstNode::dump(ostream& str) {
str<<typeName()<<" "<<(void*)this
//<<" "<<(void*)this->m_backp
<<" <e"<<dec<<editCount()
<<((editCount()>=editCountLast())?"#>":">")
<<" {"<<fileline()->filenameLetters()<<dec<<fileline()->lineno()<<"}"
<<" "<<(isSigned()?"s":"")
<<(isDouble()?"d":"")
<<"w"<<(widthSized()?"":"u")<<width();
if (!widthSized()) os<<"/"<<widthMin();
if (name()!="") os<<" "<<AstNode::quoteName(name());
<<" <e"<<dec<<editCount()
<<((editCount()>=editCountLast())?"#>":">")
<<" {"<<fileline()->filenameLetters()<<dec<<fileline()->lineno()<<"}"
<<" "<<(isSigned()?"s":"")
<<(isDouble()?"d":"")
<<"w"<<(widthSized()?"":"u")<<width();
if (!widthSized()) str<<"/"<<widthMin();
if (name()!="") str<<" "<<AstNode::quoteName(name());
}
void AstArrayDType::dump(ostream& str) {
@ -524,7 +524,7 @@ void AstAttrOf::dump(ostream& str) {
void AstBasicDType::dump(ostream& str) {
this->AstNodeDType::dump(str);
str<<" kwd="<<keyword().ascii();
if (!rangep() && msb()) str<<" range=["<<msb()<<":"<<lsb()<<"]";
if (isRanged() && !rangep()) str<<" range=["<<msb()<<":"<<lsb()<<"]";
if (implicit()) str<<" [IMPLICIT]";
}
void AstCCast::dump(ostream& str) {

2
src/V3Const.cpp
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@ -374,7 +374,7 @@ private:
if (m_warn
&& nodep->lsbp()->castConst()
&& nodep->widthp()->castConst()
&& (!bdtypep->rangep() || bdtypep->msb())) { // else it's non-resolvable parameterized
&& (!bdtypep->isRanged() || bdtypep->msb())) { // else it's non-resolvable parameterized
if (nodep->lsbp()->castConst()->num().isFourState()
|| nodep->widthp()->castConst()->num().isFourState()) {
nodep->v3error("Selection index is constantly unknown or tristated: "

1
src/V3Depth.cpp
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@ -68,6 +68,7 @@ private:
// Width, not widthMin, as we may be in middle of BITSEL expression which
// though it's one bit wide, needs the mask in the upper bits.
// (Someday we'll have a valid bitmask instead of widths....)
// See t_func_crc for an example test that requires this
AstLogicPacked(), nodep->width());
if (!m_funcp) nodep->v3fatalSrc("Deep expression not under a function");
m_funcp->addInitsp(varp);

2
src/V3EmitV.cpp
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@ -486,7 +486,7 @@ class EmitVBaseVisitor : public EmitCBaseVisitor {
if (nodep->isSigned()) putfs(nodep,"signed ");
putfs(nodep,nodep->prettyName());
if (nodep->rangep()) { puts(" "); nodep->rangep()->iterateAndNext(*this); puts(" "); }
else if (nodep->msb()) { puts(" ["); puts(cvtToStr(nodep->msb())); puts(":0] "); }
else if (nodep->isRanged()) { puts(" ["); puts(cvtToStr(nodep->msb())); puts(":0] "); }
}
virtual void visit(AstConstDType* nodep, AstNUser*) {
putfs(nodep,"const ");

7
src/V3WidthSel.cpp
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@ -144,12 +144,13 @@ private:
// Don't report WIDTH warnings etc here, as may be inside a generate branch that will be deleted
AstVar* varp = varFromBasefrom(basefromp);
// SUB #'s Not needed when LSB==0 and MSB>=0 (ie [0:-13] must still get added!)
if (!varp->basicp()->rangep()) {
if (!varp->basicp()->isRanged()) {
// vector without range, or 0 lsb is ok, for example a INTEGER x; y = x[21:0];
return underp;
} else {
if (!varp->basicp()->rangep()->msbp()->castConst()
|| !varp->basicp()->rangep()->lsbp()->castConst())
if (varp->basicp()->rangep()
&& (!varp->basicp()->rangep()->msbp()->castConst()
|| !varp->basicp()->rangep()->lsbp()->castConst()))
varp->v3fatalSrc("Non-constant variable range; errored earlier"); // in constifyParam(varp)
if (varp->basicp()->littleEndian()) {
// reg [1:3] was swapped to [3:1] (lsbEndianedp==3) and needs a SUB(3,under)

2
test_regress/t/t_case_nest.v
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@ -56,7 +56,7 @@ module sub (/*AUTOARG*/
);
input [23:0] in;
output reg [0:0] out1;
output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal
parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101;

15
test_regress/t/t_var_types.v
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@ -44,6 +44,9 @@ module t (/*AUTOARG*/);
localparam reg p_reg = {96{1'b1}};
localparam bit p_bit = {96{1'b1}};
localparam logic p_logic = {96{1'b1}};
localparam reg [0:0] p_reg1 = {96{1'b1}};
localparam bit [0:0] p_bit1 = {96{1'b1}};
localparam logic [0:0] p_logic1= {96{1'b1}};
localparam reg [1:0] p_reg2 = {96{1'b1}};
localparam bit [1:0] p_bit2 = {96{1'b1}};
localparam logic [1:0] p_logic2= {96{1'b1}};
@ -61,6 +64,9 @@ module t (/*AUTOARG*/);
function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction
function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction
function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction
function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction
function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction
function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction
function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction
function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction
function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction
@ -123,6 +129,12 @@ module t (/*AUTOARG*/);
`CHECK_P(p_bit ,1 );
`CHECK_P(p_logic ,1 );
`CHECK_P(p_reg ,1 );
`CHECK_P(p_bit1 ,1 );
`CHECK_P(p_logic1 ,1 );
`CHECK_P(p_reg1 ,1 );
`CHECK_P(p_bit1[0] ,1 );
`CHECK_P(p_logic1[0] ,1 );
`CHECK_P(p_reg1[0] ,1 );
`CHECK_P(p_bit2 ,2 );
`CHECK_P(p_logic2 ,2 );
`CHECK_P(p_reg2 ,2 );
@ -143,6 +155,9 @@ module t (/*AUTOARG*/);
`CHECK_F(f_bit ,1 ,1'b1);
`CHECK_F(f_logic ,1 ,1'b0);
`CHECK_F(f_reg ,1 ,1'b0);
`CHECK_F(f_bit1 ,1 ,1'b1);
`CHECK_F(f_logic1 ,1 ,1'b0);
`CHECK_F(f_reg1 ,1 ,1'b0);
`CHECK_F(f_bit2 ,2 ,1'b1);
`CHECK_F(f_logic2 ,2 ,1'b0);
`CHECK_F(f_reg2 ,2 ,1'b0);