verilator/test_regress/t/t_unoptflat_simple_2_bad.out

%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: Signal unoptimizable: Feedback to clock or circular logic: 't.x'
   wire [2:0] x;
              ^
                    ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
                    t/t_unoptflat_simple_2.v:14:      Example path: t.x
                    t/t_unoptflat_simple_2.v:16:      Example path: ASSIGNW
                    t/t_unoptflat_simple_2.v:14:      Example path: t.x
%Warning-UNOPTFLAT:      Widest candidate vars to split:
%Warning-UNOPTFLAT:           t/t_unoptflat_simple_2.v:14:  t.x, width 3, fanout 10
%Warning-UNOPTFLAT:      Most fanned out candidate vars to split:
%Warning-UNOPTFLAT:           t/t_unoptflat_simple_2.v:14:  t.x, width 3, fanout 10
%Error: Exiting due to