forked from github/verilator
Tests: Resolve self assignment in t_unoptflat_simple_2, Closes #2149.
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@ -14,7 +14,7 @@ module t (/*AUTOARG*/
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wire [2:0] x;
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assign x[1:0] = { x[0], clk };
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assign x[2:1] = { clk, x[1] };
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assign x[2:1] = x[1:0];
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always @(posedge clk or negedge clk) begin
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@ -22,7 +22,7 @@ module t (/*AUTOARG*/
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$write("x = %x\n", x);
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`endif
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if (x[1] != 0) begin
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if (x[2] != 0) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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@ -6,7 +6,7 @@
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t/t_unoptflat_simple_2.v:16: Example path: ASSIGNW
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t/t_unoptflat_simple_2.v:14: Example path: t.x
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%Warning-UNOPTFLAT: Widest candidate vars to split:
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%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 12
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%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 10
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%Warning-UNOPTFLAT: Most fanned out candidate vars to split:
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%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 12
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%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 10
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%Error: Exiting due to
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