verilator/test_regress/t/t_wire_beh_bad.out

%Error-CONTASSREG: t/t_wire_beh_bad.v:11: Continuous assignment to reg, perhaps intended wire (IEEE 2005 6.1; Verilog only, legal in SV): 'r'
                                        : ... In instance t
   assign r = 1'b1;
          ^
%Error-PROCASSWIRE: t/t_wire_beh_bad.v:12: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
                                         : ... In instance t
   always @ (r) w = 1'b0;
                ^
%Error: Exiting due to
In errors, single quote signals and other from-user data. 2019-07-12 02:09:30 +00:00			`%Error-CONTASSREG: t/t_wire_beh_bad.v:11: Continuous assignment to reg, perhaps intended wire (IEEE 2005 6.1; Verilog only, legal in SV): 'r'`
When showing an error, show the instance location 2019-07-26 16:52:38 +00:00			`: ... In instance t`
When showing an error, show source code. 2019-07-15 01:42:03 +00:00			`assign r = 1'b1;`
			`^`
In errors, single quote signals and other from-user data. 2019-07-12 02:09:30 +00:00			`%Error-PROCASSWIRE: t/t_wire_beh_bad.v:12: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'`
When showing an error, show the instance location 2019-07-26 16:52:38 +00:00			`: ... In instance t`
When showing an error, show source code. 2019-07-15 01:42:03 +00:00			`always @ (r) w = 1'b0;`
			`^`
Add PROCASSWIRE error on behavioral assignments to wires, msg2737. 2018-11-26 22:58:18 +00:00			`%Error: Exiting due to`