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When showing an error, show the instance location

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This commit is contained in:
Todd Strader 2019-07-26 12:52:38 -04:00
parent 5560da2934
commit 4a14788c9b
88 changed files with 488 additions and 29 deletions
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2
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@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
** When showing an error, show source code and offer suggestions of replacements.
** When showing an error, show the instance location, bug1305. [Todd Strader]
*** Add --rr, bug1481. [Todd Strader]
*** Change MULTITOP to warning to help linting, see manual.

38
src/V3Ast.cpp
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@ -1083,9 +1083,43 @@ void AstNode::v3errorEndFatal(std::ostringstream& str) const {
v3errorEnd(str); assert(0); VL_UNREACHABLE
}
string AstNode::locationStr() const {
string str = "... In instance ";
const AstNode* backp = this;
while (backp) {
const AstScope* scopep;
if ((scopep = VN_CAST_CONST(backp, Scope))) {
// The design is flattened and there are no useful scopes
// This is probably because of inilining
if (scopep->isTop()) break;
str += scopep->prettyName();
return str;
}
backp = backp->backp();
}
backp = this;
while (backp) {
const AstModule* modp;
const AstNodeVarRef* nvrp;
if ((modp = VN_CAST_CONST(backp, Module)) && !modp->hierName().empty()) {
str += modp->hierName();
return str;
} else if ((nvrp = VN_CAST_CONST(backp, NodeVarRef))) {
string prettyName = nvrp->prettyName();
// VarRefs have not been flattened yet and do not contain location information
if (prettyName != nvrp->name()) {
str += prettyName;
return str;
}
}
backp = backp->backp();
}
return "";
}
void AstNode::v3errorEnd(std::ostringstream& str) const {
if (!m_fileline) {
V3Error::v3errorEnd(str);
V3Error::v3errorEnd(str, locationStr());
} else {
std::ostringstream nsstr;
nsstr<<str.str();
@ -1095,7 +1129,7 @@ void AstNode::v3errorEnd(std::ostringstream& str) const {
const_cast<AstNode*>(this)->dump(nsstr);
nsstr<<endl;
}
m_fileline->v3errorEnd(nsstr);
m_fileline->v3errorEnd(nsstr, locationStr());
}
}

4
src/V3Ast.h
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@ -1188,6 +1188,7 @@ private:
bool ignNext, bool gateOnly);
void deleteTreeIter();
void deleteNode();
string locationStr() const;
public:
static void relinkOneLink(AstNode*& pointpr, AstNode* newp);
// cppcheck-suppress functionConst
@ -2183,6 +2184,7 @@ class AstNodeModule : public AstNode {
private:
string m_name; // Name of the module
string m_origName; // Name of the module, ignoring name() changes, for dot lookup
string m_hierName; // Hierachical name for errors, etc.
bool m_modPublic:1; // Module has public references
bool m_modTrace:1; // Tracing this module
bool m_inLibrary:1; // From a library, no error if not used, never top level
@ -2213,6 +2215,8 @@ public:
// ACCESSORS
virtual void name(const string& name) { m_name = name; }
string origName() const { return m_origName; }
string hierName() const { return m_hierName; }
void hierName(const string& hierName) { m_hierName = hierName; }
bool inLibrary() const { return m_inLibrary; }
void inLibrary(bool flag) { m_inLibrary = flag; }
void level(int level) { m_level = level; }

7
src/V3Error.cpp
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@ -161,7 +161,7 @@ string V3Error::warnMore() {
return string(msgPrefix().size(), ' ');
}
void V3Error::v3errorEnd(std::ostringstream& sstr) {
void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) {
#if defined(__COVERITY__) || defined(__cppcheck__)
if (s_errorCode==V3ErrorCode::EC_FATAL) __coverity_panic__(x);
#endif
@ -188,6 +188,11 @@ void V3Error::v3errorEnd(std::ostringstream& sstr) {
// Suppress duplicate messages
if (s_messages.find(msg) != s_messages.end()) return;
s_messages.insert(msg);
if (!locationStr.empty()) {
string locationMsg = warnMore()+locationStr+"\n";
size_t pos = msg.find("\n");
msg.insert(pos + 1, locationMsg);
}
// Output
std::cerr<<msg;
if (!s_errorSuppressed && !(s_errorCode==V3ErrorCode::EC_INFO

2
src/V3Error.h
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@ -274,7 +274,7 @@ class V3Error {
s_errorContexted = false; s_errorSuppressed = false; }
static std::ostringstream& v3errorStr() { return s_errorStr; }
static void vlAbort();
static void v3errorEnd(std::ostringstream& sstr); // static, but often overridden in classes.
static void v3errorEnd(std::ostringstream& sstr, const string& locationStr = ""); // static, but often overridden in classes.
};
// Global versions, so that if the class doesn't define a operator, we get the functions anyways.

9
src/V3FileLine.cpp
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@ -34,6 +34,7 @@
#include <algorithm>
#include <cstdarg>
#include <iomanip>
#include VL_INCLUDE_UNORDERED_SET
//######################################################################
@ -320,14 +321,18 @@ void FileLine::modifyStateInherit(const FileLine* fromp) {
}
}
void FileLine::v3errorEnd(std::ostringstream& str) {
void FileLine::v3errorEnd(std::ostringstream& str, const string& locationStr) {
std::ostringstream nsstr;
if (lastLineno()) nsstr<<this;
nsstr<<str.str();
nsstr<<endl;
std::ostringstream lstr;
if (!locationStr.empty()) {
lstr<<std::setw(ascii().length())<<" "<<": "<<locationStr;
}
if (warnIsOff(V3Error::errorCode())) V3Error::suppressThisWarning();
else if (!V3Error::errorContexted()) nsstr<<warnContextPrimary();
V3Error::v3errorEnd(nsstr);
V3Error::v3errorEnd(nsstr, lstr.str());
}
string FileLine::warnMore() const {

2
src/V3FileLine.h
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@ -225,7 +225,7 @@ public:
void modifyWarnOff(V3ErrorCode code, bool flag) { warnOff(code, flag); }
// OPERATORS
void v3errorEnd(std::ostringstream& str);
void v3errorEnd(std::ostringstream& str, const string& locationStr = "");
void v3errorEndFatal(std::ostringstream& str);
/// When building an error, prefix for printing continuation lines
/// e.g. information referring to the same FileLine as before

7
src/V3Number.cpp
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@ -49,7 +49,11 @@
void V3Number::v3errorEnd(std::ostringstream& str) const {
std::ostringstream nsstr;
nsstr<<str.str();
m_fileline->v3errorEnd(nsstr);
if (m_nodep) {
m_nodep->v3errorEnd(nsstr);
} else {
m_fileline->v3errorEnd(nsstr);
}
}
//======================================================================
@ -289,6 +293,7 @@ void V3Number::V3NumberCreate(AstNode* nodep, const char* sourcep, FileLine* fl)
}
void V3Number::setNames(AstNode* nodep) {
m_nodep = nodep;
if (!nodep) return;
m_fileline = nodep->fileline();
}

1
src/V3Number.h
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@ -42,6 +42,7 @@ class V3Number {
bool m_fromString:1; // True if from string literal
bool m_autoExtend:1; // True if SystemVerilog extend-to-any-width
FileLine* m_fileline;
AstNode* m_nodep; // Parent node
std::vector<uint32_t> m_value; // The Value, with bit 0 being in bit 0 of this vector (unless X/Z)
std::vector<uint32_t> m_valueX; // Each bit is true if it's X or Z, 10=z, 11=x
string m_stringVal; // If isString, the value of the string

28
src/V3Param.cpp
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@ -77,6 +77,7 @@ private:
// AstVar::user4() // int Global parameter number (for naming new module)
// // (0=not processed, 1=iterated, but no number,
// // 65+ parameter numbered)
// AstCell::user5p() // string* Generate portion of hierarchical name
AstUser4InUse m_inuser4;
AstUser5InUse m_inuser5;
// User1/2/3 used by constant function simulations
@ -115,6 +116,8 @@ private:
UnrollStateful m_unroller; // Loop unroller
string m_generateHierName; // Generate portion of hierarchical name
// METHODS
VL_DEBUG_FUNC; // Declare debug()
@ -219,7 +222,7 @@ private:
}
}
}
void visitCell(AstCell* nodep);
void visitCell(AstCell* nodep, const string& hierName);
void visitModules() {
// Loop on all modules left to process
// Hitting a cell adds to the appropriate level of this level-sorted list,
@ -231,6 +234,7 @@ private:
if (!nodep->user5SetOnce()) { // Process once; note clone() must clear so we do it again
m_modp = nodep;
UINFO(4," MOD "<<nodep<<endl);
if (m_modp->hierName().empty()) m_modp->hierName(m_modp->origName());
iterateChildren(nodep);
// Note above iterate may add to m_todoModps
//
@ -240,10 +244,21 @@ private:
AstCell* nodep = *it;
if ((nonIf==0 && VN_IS(nodep->modp(), Iface))
|| (nonIf==1 && !VN_IS(nodep->modp(), Iface))) {
visitCell(nodep);
string fullName (m_modp->hierName());
if (string* genHierNamep = (string *) nodep->user5p()) {
fullName += *genHierNamep;
}
visitCell(nodep, fullName);
}
}
}
for (CellList::iterator it=m_cellps.begin(); it!=m_cellps.end(); ++it) {
AstCell* cellp = *it;
if (string* genHierNamep = (string *) cellp->user5p()) {
cellp->user5p(NULL);
delete genHierNamep; VL_DANGLING(genHierNamep);
}
}
m_cellps.clear();
m_modp = NULL;
}
@ -265,6 +280,7 @@ private:
|| VN_IS(nodep, Package)) { // Likewise haven't done wrapTopPackages yet
// Add request to END of modules left to process
m_todoModps.insert(make_pair(nodep->level(), nodep));
m_generateHierName = "";
visitModules();
} else if (nodep->user5()) {
UINFO(4," MOD-done "<<nodep<<endl); // Already did it
@ -274,6 +290,8 @@ private:
}
virtual void visit(AstCell* nodep) {
// Must do ifaces first, so push to list and do in proper order
string* genHierNamep = new string(m_generateHierName);
nodep->user5p(genHierNamep);
m_cellps.push_back(nodep);
}
@ -477,7 +495,10 @@ private:
// Note this clears nodep->genforp(), so begin is no longer special
}
} else {
string rootHierName(m_generateHierName);
m_generateHierName += "." + nodep->prettyName();
iterateChildren(nodep);
m_generateHierName = rootHierName;
}
}
virtual void visit(AstGenFor* nodep) {
@ -555,7 +576,7 @@ public:
//----------------------------------------------------------------------
// VISITs
void ParamVisitor::visitCell(AstCell* nodep) {
void ParamVisitor::visitCell(AstCell* nodep, const string& hierName) {
// Cell: Check for parameters in the instantiation.
iterateChildren(nodep);
UASSERT_OBJ(nodep->modp(), nodep, "Not linked?");
@ -568,6 +589,7 @@ void ParamVisitor::visitCell(AstCell* nodep) {
// Evaluate all module constants
V3Const::constifyParamsEdit(nodep);
AstNodeModule* srcModp = nodep->modp();
srcModp->hierName(hierName + "." + nodep->name());
// Make sure constification worked
// Must be a separate loop, as constant conversion may have changed some pointers.

5
test_regress/t/t_array_backw_index_bad.out
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@ -1,16 +1,21 @@
%Error: t/t_array_backw_index_bad.v:13: Slice selection '[1:3]' has backward indexing versus data type's '[3:0]'
: ... In instance t
array_assign[1:3] = '{32'd4, 32'd3, 32'd2};
^
%Error: t/t_array_backw_index_bad.v:14: Slice selection '[3:1]' has backward indexing versus data type's '[0:3]'
: ... In instance t
larray_assign[3:1] = '{32'd4, 32'd3, 32'd2};
^
%Error: t/t_array_backw_index_bad.v:16: Slice selection index '[4:3]' outside data type's '[3:0]'
: ... In instance t
array_assign[4:3] = '{32'd4, 32'd3};
^
%Error: t/t_array_backw_index_bad.v:17: Slice selection index '[1:-1]' outside data type's '[3:0]'
: ... In instance t
array_assign[1:-1] = '{32'd4, 32'd3};
^
%Error: t/t_array_backw_index_bad.v:17: Assignment pattern missed initializing elements: -1
: ... In instance t
array_assign[1:-1] = '{32'd4, 32'd3};
^~
%Error: Exiting due to

2
test_regress/t/t_array_list_bad.out
View File

@ -1,7 +1,9 @@
%Error: t/t_array_list_bad.v:37: Assignment pattern missed initializing elements: MEMBERDTYPE 't3'
: ... In instance t
test_out <= '{'0, '0};
^~
%Warning-WIDTH: t/t_array_list_bad.v:37: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits.
: ... In instance t
test_out <= '{'0, '0};
^~
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.

1
test_regress/t/t_array_pattern_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_array_pattern_bad.v:23: Assignment pattern key 'valids' not found as member
: ... In instance t
valids: '1};
^~~~~~
%Error: Exiting due to

1
test_regress/t/t_bitsel_const_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_bitsel_const_bad.v:20: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic
: ... In instance t
assign a = b[0];
^
%Error: Exiting due to

1
test_regress/t/t_bitsel_wire_array_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_bitsel_wire_array_bad.v:20: Illegal assignment of constant to unpacked array
: ... In instance t
assign b = a[0];
^
%Error: Exiting due to

1
test_regress/t/t_case_genx_bad.out
View File

@ -1,4 +1,5 @@
%Error: t/t_case_genx_bad.v:13: Use of x/? constant in generate case statement, (no such thing as 'generate casez')
: ... In instance t
32'b1xxx: initial begin end
^~~~~~~~
%Error: Exiting due to

1
test_regress/t/t_clk_scope_bad.out
View File

@ -1,4 +1,5 @@
%Warning-CLKDATA: t/t_clk_scope_bad.v:35: Clock used as data (on rhs of assignment) in sequential block 'clk'
: ... In instance t.p2
q <= d;
^
... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message.

1
test_regress/t/t_concat_large_bad.out
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@ -1,4 +1,5 @@
%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:8: More than a 8k bit replication is probably wrong: 32768
: ... In instance t
wire [32767:0] a = {32768{1'b1}};
^
... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.

3
test_regress/t/t_const_bad.out
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@ -1,11 +1,14 @@
%Warning-WIDTH: t/t_const_bad.v:12: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
: ... In instance t
if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop;
^~~
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_const_bad.v:13: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
: ... In instance t
if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop;
^~~
%Warning-WIDTH: t/t_const_bad.v:14: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
: ... In instance t
if (68'h?_????????_???????? !== 'd?) $stop;
^~~
%Error: Exiting due to

2
test_regress/t/t_dpi_openreg_bad.out
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@ -1,7 +1,9 @@
%Error: t/t_dpi_openreg_bad.v:13: Unsized/open arrays ('[]') are only supported in DPI imports
: ... In instance t
reg a [];
^
%Error: t/t_dpi_openreg_bad.v:14: Unsized/open arrays ('[]') are only supported in DPI imports
: ... In instance t
input b [];
^
%Error: Exiting due to

1
test_regress/t/t_enum_overlap_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_enum_overlap_bad.v:11: Overlapping enumeration value: 'e1b'
: ... In instance t
e1b=1
^~~
t/t_enum_overlap_bad.v:9: ... Location of original declaration

1
test_regress/t/t_flag_werror_bad1.out
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@ -1,4 +1,5 @@
%Warning-WIDTH: t/t_flag_werror.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
: ... In instance t
wire [3:0] foo = 6'h2e;
^
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.

1
test_regress/t/t_flag_werror_bad2.out
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@ -1,4 +1,5 @@
%Error-WIDTH: t/t_flag_werror.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
: ... In instance t
wire [3:0] foo = 6'h2e;
^
%Error: Exiting due to

1
test_regress/t/t_flag_wfatal.out
View File

@ -1,4 +1,5 @@
%Warning-WIDTH: t/t_flag_wfatal.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
: ... In instance t
wire [3:0] foo = 6'h2e;
^
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.

7
test_regress/t/t_func_bad.out
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@ -1,22 +1,29 @@
%Error: t/t_func_bad.v:8: Missing argument on non-defaulted argument 'from2' in function call to FUNC 'add'
: ... In instance t
if (add(3'd1) != 0) $stop;
^~~
%Error: t/t_func_bad.v:9: Too many arguments in function call to FUNC 'add'
: ... In instance t
if (add(3'd1, 3'd2, 3'd3) != 0) $stop;
^~~~
%Error: t/t_func_bad.v:10: Missing argument on non-defaulted argument 'y' in function call to TASK 'x'
: ... In instance t
x;
^
%Error: t/t_func_bad.v:10: Unsupported: Function output argument 'y' requires 1 bits, but connection's CONST '?32?h0' generates 32 bits.
: ... In instance t
x;
^
%Error: t/t_func_bad.v:13: No such argument 'no_such' in function call to FUNC 'f'
: ... In instance t
f(.j(1), .no_such(2));
^~~~~~~
%Error: t/t_func_bad.v:14: Duplicate argument 'dup' in function call to FUNC 'f'
: ... In instance t
f(.dup(1), .dup(3));
^~~
%Error: t/t_func_bad.v:15: Too many arguments in function call to FUNC 'f'
: ... In instance t
f(1,2,3);
^
%Error: Exiting due to

1
test_regress/t/t_func_bad2.out
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@ -1,4 +1,5 @@
%Error: t/t_func_bad2.v:7: Unsupported: Recursive function or task call
: ... In instance t
function recurse;
^~~~~~~
%Error: Exiting due to

2
test_regress/t/t_func_bad_width.out
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@ -1,8 +1,10 @@
%Warning-WIDTH: t/t_func_bad_width.v:12: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits.
: ... In instance t
out = MUX (in);
^~~
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_func_bad_width.v:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits.
: ... In instance t
out = MUX (in);
^
%Error: Exiting due to

13
test_regress/t/t_func_const2_bad.out
View File

@ -1,14 +1,15 @@
%Warning-USERFATAL: "f_add = 15"
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const2_bad.v:10: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
t/t_func_const2_bad.v:21: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const2_bad.v:26: ... Called from f_add() with parameters:
%Error: t/t_func_const2_bad.v:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
: ... In instance t.b8_a7.c9
t/t_func_const2_bad.v:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const2_bad.v:14: ... Called from f_add() with parameters:
a = 32'h7
b = 32'h8
t/t_func_const2_bad.v:10: ... Called from f_add2() with parameters:
t/t_func_const2_bad.v:21: ... Called from f_add2() with parameters:
a = 32'h7
b = 32'h8
c = 32'h9
localparam P24 = f_add2(7, 8, 9);
^~~~~~
localparam SOMEP = f_add2(A, B, 9);
^~~~~~
%Error: Exiting due to

46
test_regress/t/t_func_const2_bad.v
View File

@ -3,26 +3,48 @@
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Todd Strader.
function integer f_add(input [31:0] a, input [31:0] b);
f_add = a+b;
if (f_add == 15)
$fatal(2, "f_add = 15");
endfunction
// Speced ok: function called from function
function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
f_add2 = f_add(a,b)+c;
endfunction
module c9
#(parameter A = 1,
parameter B = 1);
localparam SOMEP = f_add2(A, B, 9);
endmodule
module b8
#(parameter A = 1);
c9
#(.A (A),
.B (8))
c9;
endmodule
module t;
localparam P6 = f_add(5, 1);
localparam P14 = f_add2(2, 3, f_add(4, 5));
localparam P24 = f_add2(7, 8, 9);
//localparam P24 = f_add2(7, 8, 9);
b8 b8;
b8 #(.A (6)) b8_a6;
b8 #(.A (7)) b8_a7;
initial begin
// Should never get here
$write("*-* All Finished *-*\n");
$finish;
end
function integer f_add(input [31:0] a, input [31:0] b);
f_add = a+b;
if (f_add == 15)
$fatal(2, "f_add = 15");
endfunction
// Speced ok: function called from function
function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
f_add2 = f_add(a,b)+c;
endfunction
endmodule

6
test_regress/t/t_func_const3_bad.out Normal file
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@ -0,0 +1,6 @@
%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:11: More than a 8k bit replication is probably wrong: 9000
: ... In instance t.b9k.c9
localparam SOMEP = {BITS{1'b0}};
^
... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
%Error: Exiting due to

19
test_regress/t/t_func_const3_bad.pl Executable file
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@ -0,0 +1,19 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2017 by Todd Strader. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(simulator => 1);
compile(
v_flags2 => ["--lint-only"],
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

36
test_regress/t/t_func_const3_bad.v Normal file
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@ -0,0 +1,36 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Todd Strader.
module c9
#(parameter A = 1,
parameter B = 1);
localparam BITS = A*B;
localparam SOMEP = {BITS{1'b0}};
endmodule
module b9
#(parameter A = 1);
c9
#(.A (A),
.B (9))
c9;
endmodule
module t;
b9 b9;
b9 #(.A (100)) b900;
b9 #(.A (1000)) b9k;
initial begin
// Should never get here
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

6
test_regress/t/t_func_const_bad.out
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@ -1,26 +1,31 @@
%Error: t/t_func_const_bad.v:11: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_output'
: ... In instance t
t/t_func_const_bad.v:12: ... Location of non-constant VAR 'o': Language violation: Outputs/refs not allowed in constant functions
localparam B1 = f_bad_output(1,2);
^~~~~~~~~~~~
%Error: t/t_func_const_bad.v:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_dotted'
: ... In instance t
t/t_func_const_bad.v:22: ... Location of non-constant VARXREF 'EIGHT': Language violation: Dotted hierarchical references not allowed in constant functions
t/t_func_const_bad.v:20: ... Called from f_bad_dotted() with parameters:
a = 32'h2
localparam B2 = f_bad_dotted(2);
^~~~~~~~~~~~
%Error: t/t_func_const_bad.v:27: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_nonparam'
: ... In instance t
t/t_func_const_bad.v:29: ... Location of non-constant VARREF 'modvar': Language violation: reference to non-function-local variable
t/t_func_const_bad.v:27: ... Called from f_bad_nonparam() with parameters:
a = 32'h3
localparam B3 = f_bad_nonparam(3);
^~~~~~~~~~~~~~
%Error: t/t_func_const_bad.v:35: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_infinite'
: ... In instance t
t/t_func_const_bad.v:37: ... Location of non-constant WHILE: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024
t/t_func_const_bad.v:35: ... Called from f_bad_infinite() with parameters:
a = 32'h3
localparam B4 = f_bad_infinite(3);
^~~~~~~~~~~~~~
%Error: t/t_func_const_bad.v:43: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_stop'
: ... In instance t
t/t_func_const_bad.v:45: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_bad.v:43: ... Called from f_bad_stop() with parameters:
a = 32'h3
@ -32,6 +37,7 @@
%Warning-USERFATAL: "Fatal Error"
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const_bad.v:49: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_fatal'
: ... In instance t
t/t_func_const_bad.v:54: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_bad.v:49: ... Called from f_bad_fatal() with parameters:
a = 32'h3

1
test_regress/t/t_func_const_packed_array_bad.out
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@ -1,6 +1,7 @@
%Warning-USERFATAL: "f_add = 15"
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const_packed_array_bad.v:11: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
: ... In instance t
t/t_func_const_packed_array_bad.v:22: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_packed_array_bad.v:30: ... Called from f_add() with parameters:
params = [0 = 32'h7, 1 = 32'h8]

1
test_regress/t/t_func_const_packed_struct_bad.out
View File

@ -1,6 +1,7 @@
%Warning-USERFATAL: "f_add = 15"
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const_packed_struct_bad.v:13: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
: ... In instance t
t/t_func_const_packed_struct_bad.v:24: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_packed_struct_bad.v:32: ... Called from f_add() with parameters:
params = [0 = '{a: 32'h7, b: 32'h22b}, 1 = '{a: 32'h3039, b: 32'h8}]

1
test_regress/t/t_func_const_packed_struct_bad2.out
View File

@ -1,6 +1,7 @@
%Warning-USERFATAL: "f_add = 15"
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const_packed_struct_bad2.v:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
: ... In instance t
t/t_func_const_packed_struct_bad2.v:30: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_packed_struct_bad2.v:42: ... Called from f_add() with parameters:
params = [0 = '{a: 32'h7, foo: 6'hb, sub_params: '{b: 32'h37, bar: 8'h6f}}, 1 = '{a: 32'h3039, foo: 6'hc, sub_params: '{b: 32'h8, bar: 8'h70}}]

1
test_regress/t/t_func_const_struct_bad.out
View File

@ -1,6 +1,7 @@
%Warning-USERFATAL: "f_add = 15"
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const_struct_bad.v:16: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
: ... In instance t
t/t_func_const_struct_bad.v:27: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_struct_bad.v:37: ... Called from f_add() with parameters:
params = '{a: 32'h7, b: 32'h8}

1
test_regress/t/t_func_wide_out_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_func_wide_out_bad.v:16: Unsupported: Function output argument 'data' requires 4352 bits, but connection's VARREF 'msg' generates 4350 bits.
: ... In instance t
func(msg);
^~~
%Error: Exiting due to

4
test_regress/t/t_gen_cond_bitrange_bad.out
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@ -1,14 +1,18 @@
%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:58: Selection index out of range: 2:2 outside 1:0
: ... In instance t.i_test_gen
if ((g < (SIZE + 1)) && MASK[g]) begin
^
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:70: Selection index out of range: 2:2 outside 1:0
: ... In instance t.i_test_gen
if ((g < SIZE) && MASK[g + 1]) begin
^
%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:83: Selection index out of range: 2:2 outside 1:0
: ... In instance t.i_test_gen
if ((g < (SIZE)) & MASK[g]) begin
^
%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:96: Selection index out of range: 2:2 outside 1:0
: ... In instance t.i_test_gen
if (!((g >= SIZE) | ~MASK[g])) begin
^
%Error: Exiting due to

1
test_regress/t/t_gen_var_bad.out
View File

@ -1,4 +1,5 @@
%Error: t/t_gen_var_bad.v:9: Non-genvar used in generate for: 'i'
: ... In instance t
for (i=0; i<3; i=i+1) begin
^~~
%Error: Exiting due to

87
test_regress/t/t_generate_fatal_bad.out Normal file
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@ -0,0 +1,87 @@
%Warning-USERFATAL: "boom"
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.genloop[0].foo_inst
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'h0
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.genloop[1].foo_inst
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'h1
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.gen_l1[2].gen_l2[0].foo_inst2
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'h2
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.gen_l1[2].gen_l2[1].foo_inst2
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'h4
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.gen_l1[3].gen_l2[0].foo_inst2
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'h3
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.gen_l1[3].gen_l2[1].foo_inst2
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'h5
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.cond_true.foo_inst3
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'h6
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.genblk1.foo_inst4
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'h7
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.nested_loop[8].foo2_inst.foo2_loop[0].foo_in_foo2_inst
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'h8
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.nested_loop[8].foo2_inst.foo2_loop[1].foo_in_foo2_inst
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'h9
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.nested_loop[10].foo2_inst.foo2_loop[0].foo_in_foo2_inst
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'ha
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz'
: ... In instance t.nested_loop[10].foo2_inst.foo2_loop[1].foo_in_foo2_inst
t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters:
bar = 32'hb
localparam integer BAZ = get_baz(BAR);
^~~~~~~
%Error: Exiting due to

18
test_regress/t/t_generate_fatal_bad.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2019 by Todd Strader. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(linter => 1);
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

45
test_regress/t/t_generate_fatal_bad.v Normal file
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@ -0,0 +1,45 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
function integer get_baz(input integer bar);
get_baz = bar;
$fatal(2, "boom");
endfunction
module foo #(parameter BAR = 0);
localparam integer BAZ = get_baz(BAR);
endmodule
module foo2 #(parameter QUX = 0);
genvar x;
generate
for (x = 0; x < 2; x++) begin: foo2_loop
foo #(.BAR (QUX + x)) foo_in_foo2_inst();
end
endgenerate
endmodule
module t;
genvar i, j;
generate
for (i = 0; i < 2; i++) begin: genloop
foo #(.BAR (i)) foo_inst();
end
for (i = 2; i < 4; i++) begin: gen_l1
for (j = 0; j < 2; j++) begin: gen_l2
foo #(.BAR (i + j*2)) foo_inst2();
end
end
if (1 == 1) begin: cond_true
foo #(.BAR (6)) foo_inst3();
end
if (1 == 1) begin // unnamed
foo #(.BAR (7)) foo_inst4();
end
for (i = 8; i < 12; i = i + 2) begin: nested_loop
foo2 #(.QUX (i)) foo2_inst();
end
endgenerate
endmodule

1
test_regress/t/t_inst_array_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_inst_array_bad.v:18: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits.
: ... In instance t
sub sub [7:0] (allbits, onebitbad, bitout);
^~~~~~~~~
%Error: Exiting due to

1
test_regress/t/t_inst_misarray_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_inst_misarray_bad.v:16: VARREF 't.foo' is not an unpacked array, but is in an unpacked array context
: ... In instance t.foo
.foo(foo));
^~~
%Error: Exiting due to

4
test_regress/t/t_inst_overwide_bad.out
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@ -1,14 +1,18 @@
%Warning-WIDTH: t/t_inst_overwide.v:22: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits.
: ... In instance t
.outy_w92 (outc_w30),
^~~~~~~~
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_inst_overwide.v:23: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits.
: ... In instance t
.outz_w22 (outd_w73),
^~~~~~~~
%Warning-WIDTH: t/t_inst_overwide.v:26: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits.
: ... In instance t
.inw_w31 (ina_w1),
^~~~~~~
%Warning-WIDTH: t/t_inst_overwide.v:27: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits.
: ... In instance t
.inx_w11 (inb_w61)
^~~~~~~
%Error: Exiting due to

1
test_regress/t/t_inst_recurse2_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_inst_recurse2_bad.v:17: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped'
: ... In instance t.looped.looped
module looped ( );
^~~~~~
%Error: Exiting due to

2
test_regress/t/t_interface_array_bad.out
View File

@ -1,7 +1,9 @@
%Error: t/t_interface_array_bad.v:22: Expecting expression to be constant, but variable isn't const: 'bar'
: ... In instance t
assign foos[bar].a = 1'b1;
^~~
%Error: t/t_interface_array_bad.v:22: Could not expand constant selection inside dotted reference: 'bar'
: ... In instance t
assign foos[bar].a = 1'b1;
^
%Error: Exiting due to

4
test_regress/t/t_interface_array_nocolon_bad.out
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@ -1,14 +1,18 @@
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:25: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2
: ... In instance t
foo_intf foos [N] (.x(X));
^
... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3
: ... In instance t
foo_intf fool [1:3] (.x(X));
^
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:29: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2
: ... In instance t
foo_subm subs [N] (.x(X));
^
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3
: ... In instance t
foo_subm subl [1:3] (.x(X));
^
%Error: Exiting due to

1
test_regress/t/t_interface_param_another_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_interface_param_another_bad.v:8: Parameter-resolved constants must not use dotted references: 'dummy'
: ... In instance t
simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple();
^~~~~
%Error: Exiting due to

2
test_regress/t/t_interface_size_bad.out
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@ -1,7 +1,9 @@
%Error: t/t_interface_size_bad.v:15: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 4.
: ... In instance t
baz baz4_inst (.foo(foo4));
^~~
%Error: t/t_interface_size_bad.v:16: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 6.
: ... In instance t
baz baz6_inst (.foo(foo6));
^~~
%Error: Exiting due to

1
test_regress/t/t_interface_wrong_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_interface_wrong_bad.v:31: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface
: ... In instance t
.foo_port (bar)
^~~~~~~~
%Error: Exiting due to

4
test_regress/t/t_lint_always_comb_bad.out
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@ -1,14 +1,18 @@
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'temp1'
: ... In instance t
temp1 = 'h0;
^~~~~
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:30: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'temp1'
: ... In instance t
temp1 = (temp1_d1r - 'h1);
^~~~~
%Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:31: Always_comb variable driven after use: 'mid'
: ... In instance t
mid = (temp1_d1r == 'h0);
^~~
... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message.
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:45: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'temp1_d1r'
: ... In instance t
temp1_d1r <= temp1;
^~~~~~~~~
%Error: Exiting due to

1
test_regress/t/t_lint_ifdepth_bad.out
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@ -1,4 +1,5 @@
%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:21: Deep 'if' statement; suggest unique/priority to avoid slow logic
: ... In instance t
else if (value==11) begin end
^~
... Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message.

2
test_regress/t/t_lint_infinite.out
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@ -1,8 +1,10 @@
%Warning-INFINITELOOP: t/t_lint_infinite.v:9: Infinite loop (condition always true)
: ... In instance t
forever begin end
^~~~~~~
... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message.
%Warning-INFINITELOOP: t/t_lint_infinite.v:11: Infinite loop (condition always true)
: ... In instance t
for (reg [31:0] i=0; i>=0; i=i+1) begin end
^~~
%Error: Exiting due to

1
test_regress/t/t_lint_modport_dir_bad.out
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@ -1,4 +1,5 @@
%Error: t/t_lint_modport_dir_bad.v:25: Attempt to drive input-only modport: 'signal'
: ... In instance t.sub
assign dummy_in.signal = signal_i;
^~~~~~
%Error: Exiting due to

2
test_regress/t/t_lint_once_bad.out
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@ -1,8 +1,10 @@
%Warning-UNUSED: t/t_lint_once_bad.v:18: Signal is not driven, nor used: 'unus1'
: ... In instance t.sub3
reg [A:0] unus1; reg [A:0] unus2;
^~~~~
... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNUSED: t/t_lint_once_bad.v:18: Signal is not driven, nor used: 'unus2'
: ... In instance t.sub3
reg [A:0] unus1; reg [A:0] unus2;
^~~~~
%Error: Exiting due to

1
test_regress/t/t_lint_repeat_bad.out
View File

@ -1,4 +1,5 @@
%Warning-WIDTH: t/t_lint_repeat_bad.v:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
: ... In instance t.sub2
wire [0:0] b = a;
^
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.

1
test_regress/t/t_lint_restore_bad.out
View File

@ -1,4 +1,5 @@
%Warning-WIDTH: t/t_lint_restore_bad.v:18: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
: ... In instance t
initial five = 64'h1;
^
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.

1
test_regress/t/t_lint_setout_bad.out
View File

@ -1,4 +1,5 @@
%Error-PORTSHORT: t/t_lint_setout_bad.v:16: Output port is connected to a constant pin, electrical short
: ... In instance t
.cpu_if_timeout(1'b0)
^~~~~~~~~~~~~~
%Error: Exiting due to

1
test_regress/t/t_lint_setout_bad_noinl.out
View File

@ -1,4 +1,5 @@
%Error-PORTSHORT: t/t_lint_setout_bad.v:16: Output port is connected to a constant pin, electrical short
: ... In instance t
.cpu_if_timeout(1'b0)
^~~~~~~~~~~~~~
%Error: Exiting due to

3
test_regress/t/t_lint_subout_bad.out
View File

@ -1,10 +1,13 @@
%Error-PORTSHORT: t/t_lint_subout_bad.v:11: Output port is connected to a constant pin, electrical short
: ... In instance t
sub sub1(.out({32'b0, sig}));
^~~
%Error-PORTSHORT: t/t_lint_subout_bad.v:12: Output port is connected to a constant pin, electrical short
: ... In instance t
sub sub2(.out({32'b1, sig}));
^~~
%Error-PORTSHORT: t/t_lint_subout_bad.v:10: Output port is connected to a constant pin, electrical short
: ... In instance t
sub sub0(.out(33'b0));
^~~
%Error: Exiting due to

6
test_regress/t/t_lint_unused_bad.out
View File

@ -1,20 +1,26 @@
%Warning-UNUSED: t/t_lint_unused_bad.v:16: Bits of signal are not used: 'assunu1'[5:1]
: ... In instance t.sub
wire [5:0] assunu1 = 0;
^~~~~~~
... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNDRIVEN: t/t_lint_unused_bad.v:20: Bits of signal are not driven: 'udrb2'[14:13,11]
: ... In instance t.sub
wire [15:10] udrb2;
^~~~~
%Warning-UNUSED: t/t_lint_unused_bad.v:25: Signal is not driven, nor used: 'unu3'
: ... In instance t.sub
wire unu3;
^~~~
%Warning-UNUSED: t/t_lint_unused_bad.v:27: Bits of signal are not driven, nor used: 'mixed'[3]
: ... In instance t.sub
wire [3:0] mixed;
^~~~~
%Warning-UNUSED: t/t_lint_unused_bad.v:27: Bits of signal are not used: 'mixed'[2]
: ... In instance t.sub
wire [3:0] mixed;
^~~~~
%Warning-UNDRIVEN: t/t_lint_unused_bad.v:27: Bits of signal are not driven: 'mixed'[1]
: ... In instance t.sub
wire [3:0] mixed;
^~~~~
%Error: Exiting due to

2
test_regress/t/t_lint_unused_iface_bad.out
View File

@ -1,8 +1,10 @@
%Warning-UNDRIVEN: t/t_lint_unused_iface_bad.v:7: Signal is not driven: 'sig_udrv'
: ... In instance t.sub
logic sig_udrv;
^~~~~~~~
... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message.
%Warning-UNUSED: t/t_lint_unused_iface_bad.v:8: Signal is not used: 'sig_uusd'
: ... In instance t.sub
logic sig_uusd;
^~~~~~~~
%Error: Exiting due to

8
test_regress/t/t_lint_width_bad.out
View File

@ -1,26 +1,34 @@
%Warning-WIDTH: t/t_lint_width_bad.v:16: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.
: ... In instance t
localparam [3:0] XS = 'hx;
^~
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_lint_width_bad.v:38: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
: ... In instance t.p4
wire [4:0] out = in;
^
%Warning-WIDTH: t/t_lint_width_bad.v:20: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits.
: ... In instance t
wire [4:0] d = (1'b1 << 2) + 5'b1;
^~
%Warning-WIDTH: t/t_lint_width_bad.v:26: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits.
: ... In instance t
wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
^
%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits.
: ... In instance t
wire [2:0] cnt = (one + one + one + one);
^
%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
: ... In instance t
wire [2:0] cnt = (one + one + one + one);
^
%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
: ... In instance t
wire [2:0] cnt = (one + one + one + one);
^
%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
: ... In instance t
wire [2:0] cnt = (one + one + one + one);
^
%Error: Exiting due to

9
test_regress/t/t_mem_multi_ref_bad.out
View File

@ -1,29 +1,38 @@
%Error: t/t_mem_multi_ref_bad.v:14: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic
: ... In instance t
dimn[1:0] = 0;
^
%Error: t/t_mem_multi_ref_bad.v:14: Extracting 2 bits from only 1 bit number
: ... In instance t
dimn[1:0] = 0;
^
%Error: t/t_mem_multi_ref_bad.v:15: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic
: ... In instance t
dim0[1][1] = 0;
^
%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:15: Selection index out of range: 1:1 outside 0:0
: ... In instance t
dim0[1][1] = 0;
^
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
%Error: t/t_mem_multi_ref_bad.v:16: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic
: ... In instance t
dim1[1][1][1] = 0;
^
%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:16: Selection index out of range: 1:1 outside 0:0
: ... In instance t
dim1[1][1][1] = 0;
^
%Error: t/t_mem_multi_ref_bad.v:18: Illegal +: or -: select; type already selected, or bad dimension: type is UNPACKARRAYDTYPE
: ... In instance t
dim2[0 +: 1][1] = 0;
^
%Error: t/t_mem_multi_ref_bad.v:22: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic
: ... In instance t
dim0nv[1][1] = 0;
^
%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:22: Selection index out of range: 1:1 outside 0:0
: ... In instance t
dim0nv[1][1] = 0;
^
%Error: Exiting due to

6
test_regress/t/t_mem_slice_bad.out
View File

@ -1,19 +1,25 @@
%Error: t/t_mem_slice_bad.v:38: Slice selection index '[2:0]' outside data type's '[1:0]'
: ... In instance t
assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0];
^
%Error: t/t_mem_slice_bad.v:38: Slice selection index '[3:0]' outside data type's '[2:0]'
: ... In instance t
assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0];
^
%Error: t/t_mem_slice_bad.v:38: Slice selection index '[2:0]' outside data type's '[1:0]'
: ... In instance t
assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0];
^
%Error: t/t_mem_slice_bad.v:38: Slice selection index '[3:0]' outside data type's '[2:0]'
: ... In instance t
assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0];
^
%Error: t/t_mem_slice_bad.v:38: Slice selection index '[3:0]' outside data type's '[1:0]'
: ... In instance t
assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0];
^
%Error: t/t_mem_slice_bad.v:50: Slice selection index '[8:0]' outside data type's '[7:0]'
: ... In instance t
active_command4[7:0] <= command_A4[8:0];
^
%Error: Exiting due to

1
test_regress/t/t_param_circ_bad.out
View File

@ -1,4 +1,5 @@
%Error: t/t_param_circ_bad.v:10: Variable's initial value is circular: 'X'
: ... In instance t.sub
module sub #(parameter WIDTH=X, parameter X=WIDTH)
^
%Error: Exiting due to

3
test_regress/t/t_param_concat_bad.out
View File

@ -1,11 +1,14 @@
%Warning-WIDTHCONCAT: t/t_param_concat.v:18: Unsized numbers/parameters not allowed in concatenations.
: ... In instance t
if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop;
^~~~~~~
... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
%Warning-WIDTHCONCAT: t/t_param_concat.v:18: Unsized numbers/parameters not allowed in replications.
: ... In instance t
if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop;
^
%Warning-WIDTHCONCAT: t/t_param_concat.v:19: Unsized numbers/parameters not allowed in replications.
: ... In instance t
if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop;
^~~~~~~
%Error: Exiting due to

1
test_regress/t/t_param_default_bad.out
View File

@ -1,4 +1,5 @@
%Error: t/t_param_default_bad.v:6: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'Foo'
: ... In instance t.foo
module m #(parameter int Foo);
^~~
%Error: Exiting due to

1
test_regress/t/t_param_sel_range_bad.out
View File

@ -1,4 +1,5 @@
%Warning-SELRANGE: t/t_param_sel_range.v:40: Selection index out of range: 7:7 outside 4:0
: ... In instance t.u2
r_rst[i] <= r_rst[i-1];
^
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.

2
test_regress/t/t_past_bad.out
View File

@ -1,7 +1,9 @@
%Error: t/t_past_bad.v:11: $past tick value must be constant (IEEE 2017 16.9.3)
: ... In instance t
if ($past(d, 0)) $stop;
^~~~~
%Warning-TICKCOUNT: t/t_past_bad.v:12: $past tick value of 10000 may have a large performance cost
: ... In instance t
if ($past(d, 10000)) $stop;
^~~~~
... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message.

1
test_regress/t/t_select_bad_msb.out
View File

@ -3,6 +3,7 @@
^
... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
%Error: t/t_select_bad_msb.v:15: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1]
: ... In instance t
sel2 = mi[1:4];
^
%Error: Exiting due to

2
test_regress/t/t_select_bad_range.out
View File

@ -1,8 +1,10 @@
%Warning-SELRANGE: t/t_select_bad_range.v:15: Selection index out of range: 44:44 outside 43:0
: ... In instance t
sel = mi[44];
^
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
%Warning-SELRANGE: t/t_select_bad_range.v:16: Selection index out of range: 44:41 outside 43:0
: ... In instance t
sel2 = mi[44:41];
^
%Error: Exiting due to

1
test_regress/t/t_select_bad_range2.out
View File

@ -1,4 +1,5 @@
%Warning-SELRANGE: t/t_select_bad_range2.v:50: Selection index out of range: 3:2 outside 1:0
: ... In instance t.test
assign out32 = in[3:2];
^
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.

1
test_regress/t/t_select_bad_range3.out
View File

@ -1,4 +1,5 @@
%Warning-SELRANGE: t/t_select_bad_range3.v:18: Selection index out of range: 13 outside 12:10
: ... In instance t
assign outwires[12] = inwires[13];
^
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.

1
test_regress/t/t_select_bad_tri.out
View File

@ -1,4 +1,5 @@
%Error: t/t_select_bad_tri.v:10: Selection index is constantly unknown or tristated: lsb=7'bxxxxxxx width=32'sh47
: ... In instance t
if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop;
^
%Error: Exiting due to

1
test_regress/t/t_struct_init_bad.out
View File

@ -1,4 +1,5 @@
%Error: t/t_struct_init.v:53: Assignment pattern contains duplicate entry: b1
: ... In instance t
const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1};
^~
%Error: Exiting due to

1
test_regress/t/t_struct_notfound_bad.out
View File

@ -1,4 +1,5 @@
%Error: t/t_struct_notfound_bad.v:12: Member 'nfmember' not found in structure
: ... In instance t
s.nfmember = 0;
^~~~~~~~
%Error: Exiting due to

1
test_regress/t/t_tri_pull2_bad.out
View File

@ -1,4 +1,5 @@
%Error: t/t_tri_pull2_bad.v:9: Unsupported: Conflicting pull directions.
: ... In instance t
pullup p1(A);
^~
t/t_tri_pull2_bad.v:19: ... Location of conflicting pull.

1
test_regress/t/t_tri_pull_bad.out
View File

@ -1,4 +1,5 @@
%Error: t/t_tri_pull_bad.v:10: Unsupported: Conflicting pull directions.
: ... In instance t
pulldown p2(A);
^~
t/t_tri_pull_bad.v:9: ... Location of conflicting pull.

2
test_regress/t/t_tri_pullvec_bad.out
View File

@ -1,10 +1,12 @@
%Error: t/t_tri_pullvec_bad.v:10: Unsupported: Conflicting pull directions.
: ... In instance t
pulldown p1 (w[1]);
^~
t/t_tri_pullvec_bad.v:9: ... Location of conflicting pull.
pullup p0 (w[0]);
^~
%Error: t/t_tri_pullvec_bad.v:11: Unsupported: Conflicting pull directions.
: ... In instance t
pulldown p2 (w[2]);
^~
t/t_tri_pullvec_bad.v:9: ... Location of conflicting pull.

1
test_regress/t/t_var_const_bad.out
View File

@ -1,4 +1,5 @@
%Error: t/t_var_const_bad.v:16: Assigning to const variable: 'five'
: ... In instance t
five = 3'd4;
^~~~
%Error: Exiting due to

1
test_regress/t/t_var_ref_bad1.out
View File

@ -1,4 +1,5 @@
%Error: t/t_var_ref_bad1.v:13: Ref connection 'bad_sub_ref' requires matching types; ref requires BASICDTYPE 'real' but connection is BASICDTYPE 'bit'.
: ... In instance t
(.bad_sub_ref(bad_parent));
^~~~~~~~~~~
%Error: Exiting due to

2
test_regress/t/t_var_ref_bad2.out
View File

@ -1,7 +1,9 @@
%Error: t/t_var_ref_bad2.v:12: Assigning to const ref variable: 'bad_const_set'
: ... In instance t
bad_const_set = 32'h4567;
^~~~~~~~~~~~~
%Error: t/t_var_ref_bad2.v:22: Ref argument requires matching types; port 'int_ref' requires VAR 'int_ref' but connection is VARREF 'bad_non_int'.
: ... In instance t
checkset2(bad_non_int);
^~~~~~~~~~~
%Error: Exiting due to

1
test_regress/t/t_var_rsvd_bad.out
View File

@ -3,6 +3,7 @@
^~~~
... Use "/* verilator lint_off SYMRSVDWORD */" and lint_on around source to disable this message.
%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:14: Symbol matches C++ keyword: 'switch'
: ... In instance t
reg switch /*verilator public*/ ;
^~~~~~
%Error: Exiting due to

7
test_regress/t/t_var_types_bad.out
View File

@ -1,16 +1,21 @@
%Error: t/t_var_types_bad.v:38: Illegal bit or array select; type does not have a bit range, or bad dimension: type is bit
: ... In instance t
d_bitz[0] = 1'b1;
^
%Error: t/t_var_types_bad.v:39: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic
: ... In instance t
d_logicz[0] = 1'b1;
^
%Error: t/t_var_types_bad.v:40: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic
: ... In instance t
d_regz[0] = 1'b1;
^
%Error: t/t_var_types_bad.v:45: Illegal bit or array select; type does not have a bit range, or bad dimension: type is real
: ... In instance t
d_real[0] = 1'b1;
^
%Error: t/t_var_types_bad.v:45: Expected integral (non-real) input to SEL
: ... In instance t
d_real[0] = 1'b1;
^~~~~~
%Warning-REALCVT: t/t_var_types_bad.v:45: Implicit conversion of real to integer
@ -18,9 +23,11 @@
^~~~~~
... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.
%Error: t/t_var_types_bad.v:46: Illegal bit or array select; type does not have a bit range, or bad dimension: type is real
: ... In instance t
d_realtime[0] = 1'b1;
^
%Error: t/t_var_types_bad.v:46: Expected integral (non-real) input to SEL
: ... In instance t
d_realtime[0] = 1'b1;
^~~~~~~~~~
%Warning-REALCVT: t/t_var_types_bad.v:46: Implicit conversion of real to integer

2
test_regress/t/t_wire_beh_bad.out
View File

@ -1,7 +1,9 @@
%Error-CONTASSREG: t/t_wire_beh_bad.v:11: Continuous assignment to reg, perhaps intended wire (IEEE 2005 6.1; Verilog only, legal in SV): 'r'
: ... In instance t
assign r = 1'b1;
^
%Error-PROCASSWIRE: t/t_wire_beh_bad.v:12: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w'
: ... In instance t
always @ (r) w = 1'b0;
^
%Error: Exiting due to