Mario1159/sscs-chipathon-sar-adc
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This repository has been archived on 2023-07-29. You can view files and clone it, but cannot push or open issues or pull requests.

23 Commits
proposal ... main

Author SHA1 Message Date
Mario1159
cc9539bc85 Merge branch 'main' of https://git.1159.cl/Mario1159/sscs-chipathon-sar-adc 2023-05-08 20:47:55 -04:00
Mario1159
e87b04011c Add planification image 2023-05-08 20:47:47 -04:00
Mario Romero
95aaa1f809 Add parameter stoptime to simulation 2023-05-08 23:45:57 +00:00
Mario Romero
43d2211db1 Add ADC figure simplified 2023-05-08 04:08:31 -04:00
Mario Romero
ad55461011 Merge branch 'main' of https://git.1159.cl/Mario1159/sscs-chipathon-sar-adc 2023-05-07 18:40:37 -04:00
Mario Romero
e571e8e956 Update figures 2023-05-07 18:40:24 -04:00
Mario1159
0c61e78989 Update CDAC simulation 2023-05-07 01:21:44 -04:00
Mario1159
e4e3718dd6 Update CDAC simulations 2023-05-06 18:41:23 -04:00
Mario1159
4a5d1894fc Merge branch 'main' of https://git.1159.cl/Mario1159/sscs-chipathon-sar-adc 2023-05-05 20:28:01 -04:00
Mario1159
e3a31657cc Update verilog simulation 2023-05-05 20:27:34 -04:00
Mario Romero
c875390943 Fix m7 2023-05-02 18:32:26 -04:00
Mario Romero
9fdc94424d Change transient limits 2023-04-30 01:49:07 +00:00
Mario Romero
75c37d5ed7 Add 'spice/comp.spice' 2023-04-29 20:39:23 +00:00
Mario Romero
5de157ba5a Add tgate 2023-04-29 16:06:34 -04:00
Mario1159
c27dcf3366 Merge branch 'main' of https://git.1159.cl/Mario1159/sscs-chipathon-sar-adc 2023-04-29 15:53:40 -04:00
Mario1159
3b2ee700ec Add verilog files 2023-04-29 15:53:31 -04:00
Mario1159
5564587876 Add SAR data 2023-04-29 16:56:01 -04:00
Mario1159
c46b49af0c Add background to ADC svg 2023-04-29 16:51:50 -04:00
Mario Romero
2309c72a0f Update figure 2023-04-29 14:30:53 -04:00
Mario Romero
5ff142640c Merge branch 'main' of https://git.1159.cl/Mario1159/sscs-chipathon-sar-adc 2023-04-29 14:20:18 -04:00
Mario Romero
2003a491a2 Add labels to figures 2023-04-29 14:19:19 -04:00
Mario Romero
4d9b65ce5f Merge manually proposal (fix path) 2023-04-29 17:17:06 +00:00
Mario Romero
d5b2fb063e Add labels to switch 2023-04-29 12:46:18 -04:00
15 changed files with 1732 additions and 268 deletions
Show Stats Expand all files Collapse all files

51
data/sar/output.csv Normal file
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clk_sar,reset,Vdac_b0,Vdac_b1,Vdac_b2,Vdac_b3,Vdac_b4,Vdac_b5,Vdac_b6,Vdac_b7
0,1,x,x,x,x,x,x,x,x
1,1,0,0,0,0,0,0,0,0
0,0,0,0,0,0,0,0,0,0
1,0,0,0,0,0,0,0,0,0
0,0,0,0,0,0,0,0,0,1
1,0,0,0,0,0,0,0,0,1
0,0,0,0,0,0,0,0,1,0
1,0,0,0,0,0,0,0,1,0
0,0,0,0,0,0,0,1,0,0
1,0,0,0,0,0,0,1,0,0
0,0,0,0,0,0,1,0,0,0
1,0,0,0,0,0,1,0,0,0
0,0,0,0,0,1,0,0,0,0
1,0,0,0,0,1,0,0,0,0
0,0,0,0,1,0,0,0,0,0
1,0,0,0,1,0,0,0,0,0
0,0,0,1,1,0,0,0,0,0
1,0,0,1,1,0,0,0,0,0
0,0,1,0,1,0,0,0,0,0
1,0,1,0,1,0,0,0,0,0
0,0,1,0,1,0,0,0,0,0
1,0,1,0,1,0,0,0,0,0
0,0,0,0,0,0,0,0,0,0
1,0,0,0,0,0,0,0,0,0
0,0,0,0,0,0,0,0,0,1
1,0,0,0,0,0,0,0,0,1
0,0,0,0,0,0,0,0,1,0
1,0,0,0,0,0,0,0,1,0
0,0,0,0,0,0,0,1,0,0
1,0,0,0,0,0,0,1,0,0
0,0,0,0,0,0,1,0,0,0
1,0,0,0,0,0,1,0,0,0
0,0,0,0,0,1,0,0,0,0
1,0,0,0,0,1,0,0,0,0
0,0,0,0,1,0,0,0,0,0
1,0,0,0,1,0,0,0,0,0
0,0,0,1,1,0,0,0,0,0
1,0,0,1,1,0,0,0,0,0
0,0,1,0,1,0,0,0,0,0
1,0,1,0,1,0,0,0,0,0
0,0,1,0,1,0,0,0,0,0
1,0,1,0,1,0,0,0,0,0
0,0,0,0,0,0,0,0,0,0
1,0,0,0,0,0,0,0,0,0
0,0,0,0,0,0,0,0,0,1
1,0,0,0,0,0,0,0,0,1
0,0,0,0,0,0,0,0,1,0
1,0,0,0,0,0,0,0,1,0
0,0,0,0,0,0,0,1,0,0
1,0,0,0,0,0,0,1,0,0
1 clk_sar reset Vdac_b0 Vdac_b1 Vdac_b2 Vdac_b3 Vdac_b4 Vdac_b5 Vdac_b6 Vdac_b7
2 0 1 x x x x x x x x
3 1 1 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0 0 0
5 1 0 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0 0 1
7 1 0 0 0 0 0 0 0 0 1
8 0 0 0 0 0 0 0 0 1 0
9 1 0 0 0 0 0 0 0 1 0
10 0 0 0 0 0 0 0 1 0 0
11 1 0 0 0 0 0 0 1 0 0
12 0 0 0 0 0 0 1 0 0 0
13 1 0 0 0 0 0 1 0 0 0
14 0 0 0 0 0 1 0 0 0 0
15 1 0 0 0 0 1 0 0 0 0
16 0 0 0 0 1 0 0 0 0 0
17 1 0 0 0 1 0 0 0 0 0
18 0 0 0 1 1 0 0 0 0 0
19 1 0 0 1 1 0 0 0 0 0
20 0 0 1 0 1 0 0 0 0 0
21 1 0 1 0 1 0 0 0 0 0
22 0 0 1 0 1 0 0 0 0 0
23 1 0 1 0 1 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0
25 1 0 0 0 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 1
27 1 0 0 0 0 0 0 0 0 1
28 0 0 0 0 0 0 0 0 1 0
29 1 0 0 0 0 0 0 0 1 0
30 0 0 0 0 0 0 0 1 0 0
31 1 0 0 0 0 0 0 1 0 0
32 0 0 0 0 0 0 1 0 0 0
33 1 0 0 0 0 0 1 0 0 0
34 0 0 0 0 0 1 0 0 0 0
35 1 0 0 0 0 1 0 0 0 0
36 0 0 0 0 1 0 0 0 0 0
37 1 0 0 0 1 0 0 0 0 0
38 0 0 0 1 1 0 0 0 0 0
39 1 0 0 1 1 0 0 0 0 0
40 0 0 1 0 1 0 0 0 0 0
41 1 0 1 0 1 0 0 0 0 0
42 0 0 1 0 1 0 0 0 0 0
43 1 0 1 0 1 0 0 0 0 0
44 0 0 0 0 0 0 0 0 0 0
45 1 0 0 0 0 0 0 0 0 0
46 0 0 0 0 0 0 0 0 0 1
47 1 0 0 0 0 0 0 0 0 1
48 0 0 0 0 0 0 0 0 1 0
49 1 0 0 0 0 0 0 0 1 0
50 0 0 0 0 0 0 0 1 0 0
51 1 0 0 0 0 0 0 1 0 0

616
figures/adc.svg
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@ -1,254 +1,364 @@
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34
spice/cdac.spice
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@ -1,16 +1,18 @@
* CDAC Simulation
.include "sscs-chipathon-sar-adc/gf180mcu-pdk/libraries/gf180mcu_fd_pr/latest/models/ngspice/design.ngspice"
.lib "sscs-chipathon-sar-adc/gf180mcu-pdk/libraries/gf180mcu_fd_pr/latest/models/ngspice/sm141064.ngspice" typical
.lib "sscs-chipathon-sar-adc/gf180mcu-pdk/libraries/gf180mcu_fd_pr/latest/models/ngspice/sm141064.ngspice" mimcap_typical
.include "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/design.ngspice"
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" typical
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" mimcap_typical
.param width=10u
*.option method = gear
.param width=2.4u
* Voltage sources definition
.param vh=3.3
.param timescale=5m
.param timescale=1m
VCC ref 0 5
VCC ref 0 3.3
VD1 d1 0 PULSE(0 {vh} {1*timescale} 1p 1p {23*timescale} {25*timescale})
VD2 d2 0 PULSE(0 {vh} {2*timescale} 1p 1p {21*timescale} {25*timescale})
VD3 d3 0 PULSE(0 {vh} {3*timescale} 1p 1p {19*timescale} {25*timescale})
@ -24,15 +26,21 @@ VD10 d10 0 PULSE(0 {vh} {10*timescale} 1p 1p {5*timescale} {25*timescale})
VD11 d11 0 PULSE(0 {vh} {11*timescale} 1p 1p {3*timescale} {25*timescale})
VD12 d12 0 PULSE(0 {vh} {12*timescale} 1p 1p {1*timescale} {25*timescale})
* inv: Inverter
.subckt inv high low in out
XQP out in high high pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XQN out in low low nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
.ends inverter
* cdac_line: Capacitor controlled by switch
.subckt cdac_line in out ref_a ref_b c_width=5u c_length=5u
XQN sw_out in ref_a sw_out nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XQP sw_out in ref_b ref_b pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XI1 ref_a ref_b in in_neg inv
XI2 ref_a ref_b in_neg sw_out inv
XC1 sw_out out mim_1p5fF c_width=c_width c_length=c_length m=1
.ends cdac_line
* Components
.param cu=10u
.param cu=5u
XC0 0 outl mim_1p5fF c_width={sqrt(1)*cu} c_length={sqrt(1)*cu} m=1
XCA outl outr mim_1p5fF c_width={sqrt(1)*cu} c_length={sqrt(1)*cu} m=1
RCA outl outr 100T
@ -49,12 +57,16 @@ XD10 d10 outr ref 0 cdac_line c_width={sqrt(8)*cu} c_length={sqrt(8)*cu}
XD11 d11 outr ref 0 cdac_line c_width={sqrt(16)*cu} c_length={sqrt(16)*cu}
XD12 d12 outr ref 0 cdac_line c_width={sqrt(32)*cu} c_length={sqrt(32)*cu}
.include "param.spice"
.op
.option post nomod
.end
.tran 10u {stoptime} uic
.control
tran 10u 100m uic
run
set wr_singlescale
wrdata output.txt V(outr) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) V(d8) V(d9) V(d10) V(d11) V(d12)
.endc
.endc

62
spice/cdac_ideal.spice Normal file
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* CDAC Simulation
.include "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/design.ngspice"
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" typical
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" mimcap_typical
.option method = gear
.param width=2.4u
* Voltage sources definition
.param vh=3.3
.param timescale=5u
VCC ref 0 3.3
VD1 d1 0 PULSE({vh} 0 {1*timescale} 1p 1p {23*timescale} {25*timescale})
VD2 d2 0 PULSE({vh} 0 {2*timescale} 1p 1p {21*timescale} {25*timescale})
VD3 d3 0 PULSE({vh} 0 {3*timescale} 1p 1p {19*timescale} {25*timescale})
VD4 d4 0 PULSE({vh} 0 {4*timescale} 1p 1p {17*timescale} {25*timescale})
VD5 d5 0 PULSE({vh} 0 {5*timescale} 1p 1p {15*timescale} {25*timescale})
VD6 d6 0 PULSE({vh} 0 {6*timescale} 1p 1p {13*timescale} {25*timescale})
VD7 d7 0 PULSE({vh} 0 {7*timescale} 1p 1p {11*timescale} {25*timescale})
VD8 d8 0 PULSE({vh} 0 {8*timescale} 1p 1p {9*timescale} {25*timescale})
VD9 d9 0 PULSE({vh} 0 {9*timescale} 1p 1p {7*timescale} {25*timescale})
VD10 d10 0 PULSE({vh} 0 {10*timescale} 1p 1p {5*timescale} {25*timescale})
VD11 d11 0 PULSE({vh} 0 {11*timescale} 1p 1p {3*timescale} {25*timescale})
VD12 d12 0 PULSE({vh} 0 {12*timescale} 1p 1p {1*timescale} {25*timescale})
* cdac_line: Capacitor controlled by switch
.subckt cdac_line in out ref_a ref_b k=1
XQP sw_out in ref_a sw_out pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XQN sw_out in ref_b ref_b nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
C1 sw_out out {k*20f}
.ends cdac_line
* Components
.param cu=5u
CC0 0 outl 20f
CCA outl outr {64/63*20e-15}
RCA outl outr 100T
XD1 d1 outl ref 0 cdac_line k=1
XD2 d2 outl ref 0 cdac_line k=2
XD3 d3 outl ref 0 cdac_line k=4
XD4 d4 outl ref 0 cdac_line k=8
XD5 d5 outl ref 0 cdac_line k=16
XD6 d6 outl ref 0 cdac_line k=32
XD7 d7 outr ref 0 cdac_line k=1
XD8 d8 outr ref 0 cdac_line k=2
XD9 d9 outr ref 0 cdac_line k=4
XD10 d10 outr ref 0 cdac_line k=8
XD11 d11 outr ref 0 cdac_line k=16
XD12 d12 outr ref 0 cdac_line k=32
.op
.option post nomod
.end
.control
tran 10n 200u uic
set wr_singlescale
wrdata output.txt V(outr) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) V(d8) V(d9) V(d10) V(d11) V(d12)
.endc

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** sch_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_comp_latch_tb.sch
**.subckt adc_comp_latch_tb
V1 VDD GND 1.8
V2 clk GND 0 PULSE(0 1.8 400n 1f 1f 400n 800n)
V3 inp GND 0 PULSE({vcm-5m} {vcm+5m} 0 8u 8u 8u 16u)
V4 inn GND 0 PULSE({vcm+5m} {vcm-5m} 0 8u 8u 8u 16u)
x1 VDD GND clk inp inn comp_trig qn q adc_comp_latch
**** begin user architecture code
.param mc_mm_switch=0
.param mc_pr_switch=0
.include /content/conda-env/share/pdk/sky130A/libs.tech/ngspice/corners/tt.spice
.include /content/conda-env/share/pdk/sky130A/libs.tech/ngspice/r+c/res_typical__cap_typical.spice
.include /content/conda-env/share/pdk/sky130A/libs.tech/ngspice/r+c/res_typical__cap_typical__lin.spice
.include /content/conda-env/share/pdk/sky130A/libs.tech/ngspice/corners/tt/specialized_cells.spice
.save all
.temp 25
.OPTIONS RELTOL=.001 TRTOL=1 ABSTOL=1e-16 CHGTOL=1.0e-16 DEFAD=1.0e-16
.param vcm=900m
.control
tran 100p 4.403u 4.3995u
set wr_singlescale
wrdata plot1.txt v(inp)-v(inn)
wrdata plot2.txt v(q) v(comp_trig)
wrdata delay.txt v(clk) v(comp_trig) v(q)
wrdata plot4.txt v(x1.x1.on) v(x1.x1.op)
wrdata plot5.txt v(x1.x1.bn) v(x1.x1.bp)
.endc
**** end user architecture code
**.ends
* expanding symbol: adc_comp_latch.sym # of pins=8
** sym_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_comp_latch.sym
** sch_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_comp_latch.sch
.subckt adc_comp_latch VDD VSS clk inp inn comp_trig latch_qn latch_q
*.iopin VDD
*.iopin VSS
*.ipin clk
*.ipin inp
*.ipin inn
*.opin comp_trig
*.opin latch_qn
*.opin latch_q
x4 VDD VSS clk net1 adc_inverter
x5 VDD VSS net1 net2 adc_inverter
x1 VDD VSS net2 net1 inp inn comp_outp comp_outn adc_comp_circuit
x3 comp_outp comp_outn VDD comp_trig VSS adc_nor
x2 comp_outp latch_qn VDD latch_q VSS comp_outn adc_nor_latch
.ends
* expanding symbol: adc_inverter.sym # of pins=4
** sym_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_inverter.sym
** sch_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_inverter.sch
.subckt adc_inverter VDD VSS in out
*.iopin VDD
*.iopin VSS
*.ipin in
*.opin out
XM2 out in VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.84 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM1 out in VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
.ends
* expanding symbol: adc_comp_circuit.sym # of pins=8
** sym_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_comp_circuit.sym
** sch_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_comp_circuit.sch
.subckt adc_comp_circuit VPWR VGND clk nclk inp inn outp outn
*.iopin VPWR
*.iopin VGND
*.ipin clk
*.ipin nclk
*.ipin inp
*.ipin inn
*.opin outp
*.opin outn
XM3 on inp in_stage_net1 VGND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=8 nf=4 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM4 op inn in_stage_net1 VGND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=8 nf=4 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM5 in_stage_net1 clk VGND VGND sky130_fd_pr__nfet_01v8 L=0.15 W=4 nf=8 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM6 in_stage_net2 bp VPWR VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=2 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM7 in_stage_net3 bn VPWR VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=2 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM8 bn op in_stage_net2 VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=2 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM9 bp on in_stage_net3 VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=4 nf=2 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM10 bn bp VGND VGND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM11 bn nclk VGND VGND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM12 bp nclk VGND VGND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM13 bp bn VGND VGND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM2 op clk VPWR VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=4 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM1 on clk VPWR VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=4 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
x1 VPWR VGND bp outp adc_comp_buffer
x2 VPWR VGND bn outn adc_comp_buffer
x3 VGND VGND on VGND VGND adc_noise_decoup_cell2
x4 VGND VGND op VGND VGND adc_noise_decoup_cell2
XM4_DUMMY in_stage_net1 inn in_stage_net1 VGND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM3_DUMMY in_stage_net1 inp in_stage_net1 VGND sky130_fd_pr__nfet_01v8_lvt L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM5_DUMMY2 in_stage_net1 clk in_stage_net1 VGND sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM5_DUMMY1 in_stage_net1 clk in_stage_net1 VGND sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM2_DUMMY VPWR clk VPWR VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM1_DUMMY VPWR clk VPWR VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM8_DUMMY in_stage_net2 op in_stage_net2 VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM9_DUMMY in_stage_net3 on in_stage_net3 VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM6_DUMMY in_stage_net2 bp in_stage_net2 VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM7_DUMMY in_stage_net3 bn in_stage_net3 VPWR sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM12_DUMMY VGND VGND VGND VGND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
XM11_DUMMY VGND VGND VGND VGND sky130_fd_pr__nfet_01v8 L=0.15 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
.ends
* expanding symbol: adc_nor.sym # of pins=5
** sym_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_nor.sym
** sch_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_nor.sch
.subckt adc_nor b a VDD q VSS
*.iopin VDD
*.iopin VSS
*.ipin b
*.ipin a
*.opin q
XM5 q b VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM6 q a VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=0.42 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM1 q b net1 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM2 q a net2 VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM3 net2 b VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM4 net1 a VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=0.8 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
.ends
* expanding symbol: adc_nor_latch.sym # of pins=6
** sym_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_nor_latch.sym
** sch_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_nor_latch.sch
.subckt adc_nor_latch s qn VDD q VSS r
*.iopin VDD
*.iopin VSS
*.ipin s
*.ipin r
*.opin q
*.opin qn
x1 q s VDD qn VSS adc_nor
x2 qn r VDD q VSS adc_nor
.ends
* expanding symbol: adc_comp_buffer.sym # of pins=4
** sym_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_comp_buffer.sym
** sch_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_comp_buffer.sch
.subckt adc_comp_buffer VDD VSS in out
*.iopin VDD
*.iopin VSS
*.ipin in
*.opin out
XM5 buf_mid in VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=0.5 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM1 buf_mid in VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM2 out buf_mid VDD VDD sky130_fd_pr__pfet_01v8 L=0.15 W=2 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
XM6 out buf_mid VSS VSS sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
+ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W'
+ sa=0 sb=0 sd=0 mult=1 m=1
.ends
* expanding symbol: adc_noise_decoup_cell2.sym # of pins=5
** sym_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_noise_decoup_cell2.sym
** sch_path: /foss/designs/personal/SKY130_SAR-ADC/xschem/adc_noise_decoup_cell2.sch
.subckt adc_noise_decoup_cell2 mimcap_top mimcap_bot nmoscap_top nmoscap_bot pwell
*.iopin nmoscap_top
*.iopin mimcap_top
*.iopin mimcap_bot
*.iopin nmoscap_bot
*.iopin pwell
XC1 mimcap_top mimcap_bot sky130_fd_pr__cap_mim_m3_1 W=18.9 L=5.1 MF=1 m=1
XC2 nmoscap_top nmoscap_bot pwell sky130_fd_pr__cap_var_lvt W=18.4 L=3.9 VM=1 m=1
.ends
.GLOBAL GND
.GLOBAL VDD
.end

46
verilog/rtl/Code_Register.v Normal file
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module Code_Register #(parameter N_bits=4)(
input comparator_out , rst,
input [N_bits + 1 : 0]shift_register_out,
output wire [N_bits -1 : 0]data_register_out
);
reg [N_bits : 0]data_register ;
// Estos flip flop son los Registros del mas significativo al penultimo mas significativo
for ( genvar i = 0 ; i<= N_bits-1 ; i = i + 1) begin
always @(posedge data_register[i + 1] or posedge shift_register_out[i+1] or posedge rst ) begin
if(rst)
data_register[i] <= 'd0 ;
else if (shift_register_out[i + 1])
data_register[i]<= 'd1 ;
else begin
data_register[i] <= comparator_out ;
end
end
end
// ahora se pone el caso extremo que es para analziar el utimo bit ques el LSB
always @(posedge shift_register_out[N_bits + 1] or posedge rst) begin
if(rst)
data_register[N_bits] = 'd0 ;
else
data_register[N_bits] = 'd1 ;
end
// always@ (posedge shift_register_out[0]) begin
// if(rst)
// data_register <= 'd0 ;
// else if (shift_register_out[0])
// data_register<= 'd0 ;
// end
assign data_register_out =data_register [N_bits - 1 : 0] ;
endmodule

25
verilog/rtl/Sequencer_Register.v Normal file
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module Sequencer_Register #(parameter N_bits=4)(
input clk_sar , rst,
output wire EOC,
output wire [N_bits + 1 : 0]shift_register_out
);
// el numero de register que hay para activar los bits de salida correspondiente son N_bits + 2 para este sistema funcione bien
reg [N_bits + 1 :0] shift_register;
always @(posedge clk_sar) begin
if (rst) begin
shift_register[N_bits + 1 : 1 ] <= 'd0;
shift_register[0] <= 'd1;
end else begin
shift_register <= { shift_register[N_bits : 0] , shift_register[N_bits + 1] };
end
end
assign EOC = shift_register[N_bits + 1] ;
assign shift_register_out = shift_register[N_bits + 1 : 0] ;
endmodule

90
verilog/tb/SAR_SIM.sv Normal file
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module SAR_SIM( );
localparam N_bits = 8 ;
reg clk_sar ;
reg reset ;
wire EOC ;
wire [N_bits +1 : 0 ] shift_register_out ;
Sequencer_Register #(N_bits) seq_sim (
.clk_sar(clk_sar) ,
.rst(reset),
.EOC(EOC),
.shift_register_out(shift_register_out)
);
reg comparator_out ;
wire [N_bits -1 : 0]data_register_out ;
Code_Register #(N_bits) Code_sim (
.comparator_out(comparator_out),
.rst(reset),
.shift_register_out(shift_register_out),
.data_register_out(data_register_out)
);
//CLK sample y CLK sar
always #1 clk_sar = ~clk_sar ;
wire [N_bits-1 : 0] Vin ;
wire [N_bits-1 : 0] Vdac ;
assign Vin = 'd5 ;
assign Vdac = {data_register_out[0 ] , data_register_out[ 1] , data_register_out[2 ] , data_register_out[ 3] , data_register_out[ 4] , data_register_out[ 5] , data_register_out[ 6] , data_register_out[ 7]} ;
always @(*) begin
if(Vin >= Vdac )
comparator_out = 'd1 ;
else
comparator_out = 'd0 ;
end
always @(*) begin
if (EOC) begin
reset = 'd1 ;
#1
reset = 'd0 ;
end
end
initial begin
clk_sar = 0 ;
reset = 1 ;
#2
reset = 0 ;
#100
$finish ;
end
initial begin
$dumpfile("Code_Reg_Out.txt") ;
$dumpvars(0);
end
integer f , i ;
initial begin
f = $fopen("output.csv", "w");
$fwrite(f, "clk_sar,reset,Vdac_b0,Vdac_b1,Vdac_b2,Vdac_b3,Vdac_b4,Vdac_b5,Vdac_b6,Vdac_b7\n");
for (i=0; i<102; i++) begin
//$fwrite(f, "%d,%d,%d,%d,%d,%d,%d\n", clk_sar , reset ,Vdac , Vin ,shift_register_out , data_register_out , comparator_out );
$fwrite(f, "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n", clk_sar,reset,Vdac[0],Vdac[1],Vdac[2],Vdac[3],Vdac[4],Vdac[5],Vdac[6],Vdac[7] );
#1;
end
$fclose(f) ;
$finish ;
end
endmodule