73 lines
3.1 KiB
Plaintext
73 lines
3.1 KiB
Plaintext
* CDAC Simulation
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.include "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/design.ngspice"
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.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" typical
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.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" mimcap_typical
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*.option method = gear
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.param width=2.4u
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* Voltage sources definition
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.param vh=3.3
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.param timescale=1m
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VCC ref 0 3.3
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VD1 d1 0 PULSE(0 {vh} {1*timescale} 1p 1p {23*timescale} {25*timescale})
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VD2 d2 0 PULSE(0 {vh} {2*timescale} 1p 1p {21*timescale} {25*timescale})
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VD3 d3 0 PULSE(0 {vh} {3*timescale} 1p 1p {19*timescale} {25*timescale})
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VD4 d4 0 PULSE(0 {vh} {4*timescale} 1p 1p {17*timescale} {25*timescale})
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VD5 d5 0 PULSE(0 {vh} {5*timescale} 1p 1p {15*timescale} {25*timescale})
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VD6 d6 0 PULSE(0 {vh} {6*timescale} 1p 1p {13*timescale} {25*timescale})
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VD7 d7 0 PULSE(0 {vh} {7*timescale} 1p 1p {11*timescale} {25*timescale})
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VD8 d8 0 PULSE(0 {vh} {8*timescale} 1p 1p {9*timescale} {25*timescale})
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VD9 d9 0 PULSE(0 {vh} {9*timescale} 1p 1p {7*timescale} {25*timescale})
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VD10 d10 0 PULSE(0 {vh} {10*timescale} 1p 1p {5*timescale} {25*timescale})
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VD11 d11 0 PULSE(0 {vh} {11*timescale} 1p 1p {3*timescale} {25*timescale})
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VD12 d12 0 PULSE(0 {vh} {12*timescale} 1p 1p {1*timescale} {25*timescale})
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* inv: Inverter
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.subckt inv high low in out
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XQP out in high high pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
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XQN out in low low nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
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.ends inverter
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* cdac_line: Capacitor controlled by switch
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.subckt cdac_line in out ref_a ref_b c_width=5u c_length=5u
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XI1 ref_a ref_b in in_neg inv
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XI2 ref_a ref_b in_neg sw_out inv
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XC1 sw_out out mim_1p5fF c_width=c_width c_length=c_length m=1
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.ends cdac_line
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* Components
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.param cu=5u
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XC0 0 outl mim_1p5fF c_width={sqrt(1)*cu} c_length={sqrt(1)*cu} m=1
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XCA outl outr mim_1p5fF c_width={sqrt(1)*cu} c_length={sqrt(1)*cu} m=1
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RCA outl outr 100T
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XD1 d1 outl ref 0 cdac_line c_width={sqrt(1)*cu} c_length={sqrt(1)*cu}
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XD2 d2 outl ref 0 cdac_line c_width={sqrt(2)*cu} c_length={sqrt(2)*cu}
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XD3 d3 outl ref 0 cdac_line c_width={sqrt(4)*cu} c_length={sqrt(4)*cu}
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XD4 d4 outl ref 0 cdac_line c_width={sqrt(8)*cu} c_length={sqrt(8)*cu}
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XD5 d5 outl ref 0 cdac_line c_width={sqrt(16)*cu} c_length={sqrt(16)*cu}
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XD6 d6 outl ref 0 cdac_line c_width={sqrt(32)*cu} c_length={sqrt(32)*cu}
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XD7 d7 outr ref 0 cdac_line c_width={sqrt(1)*cu} c_length={sqrt(1)*cu}
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XD8 d8 outr ref 0 cdac_line c_width={sqrt(2)*cu} c_length={sqrt(2)*cu}
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XD9 d9 outr ref 0 cdac_line c_width={sqrt(4)*cu} c_length={sqrt(4)*cu}
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XD10 d10 outr ref 0 cdac_line c_width={sqrt(8)*cu} c_length={sqrt(8)*cu}
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XD11 d11 outr ref 0 cdac_line c_width={sqrt(16)*cu} c_length={sqrt(16)*cu}
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XD12 d12 outr ref 0 cdac_line c_width={sqrt(32)*cu} c_length={sqrt(32)*cu}
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.include "param.spice"
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.op
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.option post nomod
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.end
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.tran 10u {stoptime} uic
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.control
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run
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set wr_singlescale
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wrdata output.txt V(outr) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) V(d8) V(d9) V(d10) V(d11) V(d12)
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.endc
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