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Update CDAC simulations

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This commit is contained in:
Mario Romero 2023-05-06 18:41:23 -04:00
parent 4a5d1894fc
commit e4e3718dd6
2 changed files with 84 additions and 20 deletions
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42
spice/cdac.spice
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@ -4,35 +4,37 @@
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" typical
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" mimcap_typical
.param width=10u
.option method = gear
.param width=2.4u
* Voltage sources definition
.param vh=3.3
.param timescale=5m
.param timescale=5u
VCC ref 0 5
VD1 d1 0 PULSE(0 {vh} {1*timescale} 1p 1p {23*timescale} {25*timescale})
VD2 d2 0 PULSE(0 {vh} {2*timescale} 1p 1p {21*timescale} {25*timescale})
VD3 d3 0 PULSE(0 {vh} {3*timescale} 1p 1p {19*timescale} {25*timescale})
VD4 d4 0 PULSE(0 {vh} {4*timescale} 1p 1p {17*timescale} {25*timescale})
VD5 d5 0 PULSE(0 {vh} {5*timescale} 1p 1p {15*timescale} {25*timescale})
VD6 d6 0 PULSE(0 {vh} {6*timescale} 1p 1p {13*timescale} {25*timescale})
VD7 d7 0 PULSE(0 {vh} {7*timescale} 1p 1p {11*timescale} {25*timescale})
VD8 d8 0 PULSE(0 {vh} {8*timescale} 1p 1p {9*timescale} {25*timescale})
VD9 d9 0 PULSE(0 {vh} {9*timescale} 1p 1p {7*timescale} {25*timescale})
VD10 d10 0 PULSE(0 {vh} {10*timescale} 1p 1p {5*timescale} {25*timescale})
VD11 d11 0 PULSE(0 {vh} {11*timescale} 1p 1p {3*timescale} {25*timescale})
VD12 d12 0 PULSE(0 {vh} {12*timescale} 1p 1p {1*timescale} {25*timescale})
VCC ref 0 3.3
VD1 d1 0 PULSE({vh} 0 {1*timescale} 1p 1p {23*timescale} {25*timescale})
VD2 d2 0 PULSE({vh} 0 {2*timescale} 1p 1p {21*timescale} {25*timescale})
VD3 d3 0 PULSE({vh} 0 {3*timescale} 1p 1p {19*timescale} {25*timescale})
VD4 d4 0 PULSE({vh} 0 {4*timescale} 1p 1p {17*timescale} {25*timescale})
VD5 d5 0 PULSE({vh} 0 {5*timescale} 1p 1p {15*timescale} {25*timescale})
VD6 d6 0 PULSE({vh} 0 {6*timescale} 1p 1p {13*timescale} {25*timescale})
VD7 d7 0 PULSE({vh} 0 {7*timescale} 1p 1p {11*timescale} {25*timescale})
VD8 d8 0 PULSE({vh} 0 {8*timescale} 1p 1p {9*timescale} {25*timescale})
VD9 d9 0 PULSE({vh} 0 {9*timescale} 1p 1p {7*timescale} {25*timescale})
VD10 d10 0 PULSE({vh} 0 {10*timescale} 1p 1p {5*timescale} {25*timescale})
VD11 d11 0 PULSE({vh} 0 {11*timescale} 1p 1p {3*timescale} {25*timescale})
VD12 d12 0 PULSE({vh} 0 {12*timescale} 1p 1p {1*timescale} {25*timescale})
* cdac_line: Capacitor controlled by switch
.subckt cdac_line in out ref_a ref_b c_width=5u c_length=5u
XQN sw_out in ref_a sw_out nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XQP sw_out in ref_b ref_b pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XQP sw_out in ref_a sw_out pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XQN sw_out in ref_b ref_b nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XC1 sw_out out mim_1p5fF c_width=c_width c_length=c_length m=1
.ends cdac_line
* Components
.param cu=10u
.param cu=5u
XC0 0 outl mim_1p5fF c_width={sqrt(1)*cu} c_length={sqrt(1)*cu} m=1
XCA outl outr mim_1p5fF c_width={sqrt(1)*cu} c_length={sqrt(1)*cu} m=1
RCA outl outr 100T
@ -54,7 +56,7 @@ XD12 d12 outr ref 0 cdac_line c_width={sqrt(32)*cu} c_length={sqrt(32)*cu}
.end
.control
tran 10u 100m uic
tran 10n 200u uic
set wr_singlescale
wrdata output.txt V(outr) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) V(d8) V(d9) V(d10) V(d11) V(d12)
.endc
.endc

62
spice/cdac_ideal.spice Normal file
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@ -0,0 +1,62 @@
* CDAC Simulation
.include "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/design.ngspice"
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" typical
.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" mimcap_typical
.option method = gear
.param width=2.4u
* Voltage sources definition
.param vh=3.3
.param timescale=5u
VCC ref 0 3.3
VD1 d1 0 PULSE({vh} 0 {1*timescale} 1p 1p {23*timescale} {25*timescale})
VD2 d2 0 PULSE({vh} 0 {2*timescale} 1p 1p {21*timescale} {25*timescale})
VD3 d3 0 PULSE({vh} 0 {3*timescale} 1p 1p {19*timescale} {25*timescale})
VD4 d4 0 PULSE({vh} 0 {4*timescale} 1p 1p {17*timescale} {25*timescale})
VD5 d5 0 PULSE({vh} 0 {5*timescale} 1p 1p {15*timescale} {25*timescale})
VD6 d6 0 PULSE({vh} 0 {6*timescale} 1p 1p {13*timescale} {25*timescale})
VD7 d7 0 PULSE({vh} 0 {7*timescale} 1p 1p {11*timescale} {25*timescale})
VD8 d8 0 PULSE({vh} 0 {8*timescale} 1p 1p {9*timescale} {25*timescale})
VD9 d9 0 PULSE({vh} 0 {9*timescale} 1p 1p {7*timescale} {25*timescale})
VD10 d10 0 PULSE({vh} 0 {10*timescale} 1p 1p {5*timescale} {25*timescale})
VD11 d11 0 PULSE({vh} 0 {11*timescale} 1p 1p {3*timescale} {25*timescale})
VD12 d12 0 PULSE({vh} 0 {12*timescale} 1p 1p {1*timescale} {25*timescale})
* cdac_line: Capacitor controlled by switch
.subckt cdac_line in out ref_a ref_b k=1
XQP sw_out in ref_a sw_out pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
XQN sw_out in ref_b ref_b nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
C1 sw_out out {k*20f}
.ends cdac_line
* Components
.param cu=5u
CC0 0 outl 20f
CCA outl outr {64/63*20e-15}
RCA outl outr 100T
XD1 d1 outl ref 0 cdac_line k=1
XD2 d2 outl ref 0 cdac_line k=2
XD3 d3 outl ref 0 cdac_line k=4
XD4 d4 outl ref 0 cdac_line k=8
XD5 d5 outl ref 0 cdac_line k=16
XD6 d6 outl ref 0 cdac_line k=32
XD7 d7 outr ref 0 cdac_line k=1
XD8 d8 outr ref 0 cdac_line k=2
XD9 d9 outr ref 0 cdac_line k=4
XD10 d10 outr ref 0 cdac_line k=8
XD11 d11 outr ref 0 cdac_line k=16
XD12 d12 outr ref 0 cdac_line k=32
.op
.option post nomod
.end
.control
tran 10n 200u uic
set wr_singlescale
wrdata output.txt V(outr) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) V(d8) V(d9) V(d10) V(d11) V(d12)
.endc