Add verilog files

verilog/rtl/Code_Register.v

@@ -0,0 +1,46 @@
+module Code_Register #(parameter N_bits=4)(
+        input  comparator_out , rst, 
+        input [N_bits + 1 : 0]shift_register_out,
+        output wire [N_bits -1 : 0]data_register_out
+    );
+
+ 
+ reg [N_bits : 0]data_register ; 
+
+ // Estos flip flop son los Registros del mas significativo al penultimo mas significativo
+
+for ( genvar i = 0 ;  i<= N_bits-1  ; i = i + 1) begin 
+            always @(posedge data_register[i + 1] or posedge shift_register_out[i+1] or posedge rst ) begin
+                    if(rst)
+                        data_register[i] <= 'd0 ; 
+                    else if (shift_register_out[i + 1])
+                        data_register[i]<= 'd1 ; 
+                    else begin 
+                        data_register[i] <= comparator_out ;
+                    end
+            end
+    end
+
+// ahora se pone el caso extremo que es para analziar el utimo bit ques el LSB 
+
+always @(posedge  shift_register_out[N_bits + 1] or posedge rst) begin
+        if(rst)
+            data_register[N_bits] = 'd0 ; 
+        else
+            data_register[N_bits] = 'd1 ; 
+
+end
+
+always@ (posedge shift_register_out[0]) begin 
+         if(rst)
+            data_register <= 'd0 ; 
+        else if (shift_register_out[0])
+             data_register<= 'd0 ; 
+
+end
+
+assign data_register_out =data_register [N_bits - 1 : 0] ; 
+
+endmodule
+
+

verilog/rtl/Sequencer_Register.v

@@ -0,0 +1,25 @@
+module Sequencer_Register #(parameter N_bits=4)(
+        input  clk_sar , rst,
+        output wire  EOC,
+        output wire [N_bits + 1 : 0]shift_register_out
+
+    );
+
+    // el numero de register que hay para activar los bits de salida correspondiente  son N_bits + 2 para este sistema funcione bien 
+
+    reg  [N_bits + 1 :0] shift_register;
+
+    always @(posedge clk_sar) begin
+        if (rst) begin
+            shift_register[N_bits + 1 : 1 ] <= 'd0;
+            shift_register[0] <= 'd1;
+        end else begin
+            shift_register <= { shift_register[N_bits : 0] , shift_register[N_bits + 1] };
+        end
+  end
+
+
+  assign EOC = shift_register[N_bits + 1] ; 
+  assign shift_register_out = shift_register[N_bits + 1 : 0] ; 
+
+endmodule

verilog/tb/SAR_SIM.sv

@@ -0,0 +1,81 @@
+module SAR_SIM( );
+
+localparam N_bits = 8 ;
+reg clk_sar ;
+reg reset ;
+wire EOC ;
+wire [N_bits +1 : 0 ] shift_register_out  ;
+
+Sequencer_Register  #(N_bits) seq_sim (
+    .clk_sar(clk_sar) , 
+    .rst(reset),
+    .EOC(EOC),
+    .shift_register_out(shift_register_out) 
+);
+
+reg comparator_out ;
+wire [N_bits -1 : 0]data_register_out ;
+
+Code_Register #(N_bits) Code_sim (
+        .comparator_out(comparator_out),
+         .rst(reset), 
+        .shift_register_out(shift_register_out),
+        .data_register_out(data_register_out)
+    );
+
+//CLK sample y CLK sar
+always  #1 clk_sar = ~clk_sar ; 
+
+
+
+
+
+wire [N_bits-1 : 0] Vin ; 
+wire [N_bits-1 : 0] Vdac ; 
+assign Vin = 'd5 ; 
+
+assign Vdac = {data_register_out[0 ] , data_register_out[ 1] , data_register_out[2 ] , data_register_out[ 3] , data_register_out[ 4] , data_register_out[ 5] , data_register_out[ 6] , data_register_out[ 7]} ;
+
+always @(*) begin
+    if(Vin >= Vdac )
+        comparator_out = 'd1 ;
+    else
+         comparator_out = 'd0 ;
+
+end
+
+
+initial begin
+    clk_sar = 0 ;
+    reset = 1 ; 
+
+    #2
+    reset = 0 ;
+
+    #50
+    $finish ;
+
+end
+
+
+initial begin 
+    $dumpfile("Code_Reg_Out.txt") ; 
+    $dumpvars(0); 
+
+end 
+
+integer  f , i ;
+initial begin
+    f = $fopen("output.csv", "w");
+    $fwrite(f, "clk_sar,reset,Vdac_b0,Vdac_b1,Vdac_b2,Vdac_b3,Vdac_b4,Vdac_b5,Vdac_b6,Vdac_b7\n");
+    for (i=0; i<50; i++) begin 
+        //$fwrite(f, "%d,%d,%d,%d,%d,%d,%d\n", clk_sar , reset ,Vdac , Vin ,shift_register_out , data_register_out , comparator_out );
+        $fwrite(f, "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n", clk_sar,reset,Vdac[0],Vdac[1],Vdac[2],Vdac[3],Vdac[4],Vdac[5],Vdac[6],Vdac[7] );
+        #1; 
+    end
+    $fclose(f) ;
+    $finish ;
+end
+
+
+endmodule