8 _Sidebar

Mario Romero edited this page 2023-08-07 19:52:07 +00:00

Table of Contents

• Table of Contents

Table of Contents

• General Architecture
  • Datapaths
    • Single-Cycle
    • 5-Stage Multi-Cycle
    • 5-Stage Pipelined
  • Datapath units
    • Instruction Memory
    • ALU
    • Extend
    • Register File
  • Interfaces
    • Instruction Memory Interface
    • Data Memory Interface
    • AXI4
• Verification

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