6 ALU

Mario Romero edited this page 2023-06-06 16:43:01 +00:00

Table of Contents

• Arithmetic Logic Unit (ALU)

Arithmetic Logic Unit (ALU)

Defined in rtl/alu.sv

Figure	Direction	Signal
	Input	a
		b
		operation
	Output	result
		status

The Arithmetic Logic Unit (ALU) is the combinatorial circuit in charge to perform the binary operation selected by the operation signal.

alu_opcode_t is the enum that represent the operations, these are defined in rv32i_defs.sv.

The status bus represent the following flags:

Bit index	Flag	Description
0	N	Result is negative
1	Z	Result is zero
2	C	Carry out
3	V	Overflow

Table of Contents

• General Architecture
  • Datapaths
    • Single-Cycle
    • 5-Stage Multi-Cycle
    • 5-Stage Pipelined
  • Datapath units
    • Instruction Memory
    • ALU
    • Extend
    • Register File
  • Interfaces
    • Instruction Memory Interface
    • Data Memory Interface
    • AXI4
• Verification

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