3 Five-Stage-Pipelined-Datapath

Mario Romero edited this page 2023-08-07 18:31:51 +00:00

The five stages of the pipeline are:

• Fetch
• Decode
• Execute
• Memory
• Writeback

The circuit diagram is similar to the one explained in the book "Digital Design and Computer Architecture" by Sarah & David Harris

TODO: Add datapath figure

Table of Contents

• General Architecture
  • Datapaths
    • Single-Cycle
    • 5-Stage Multi-Cycle
    • 5-Stage Pipelined
  • Datapath units
    • Instruction Memory
    • ALU
    • Extend
    • Register File
  • Interfaces
    • Instruction Memory Interface
    • Data Memory Interface
    • AXI4
• Verification

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