1 Register File

Mario Romero edited this page 2023-08-07 19:51:31 +00:00

Table of Contents

• Register File

Register File

Defined in rtl/register_file.sv

Figure	Direction	Signal
	Input	clk
		rst
		addr_1
		addr_2
		addr_3
		write_enable_3
	Output	read_data_1
		read_data_2

32-bit register container using synchronous reset and write_enable states.

Table of Contents

• General Architecture
  • Datapaths
    • Single-Cycle
    • 5-Stage Multi-Cycle
    • 5-Stage Pipelined
  • Datapath units
    • Instruction Memory
    • ALU
    • Extend
    • Register File
  • Interfaces
    • Instruction Memory Interface
    • Data Memory Interface
    • AXI4
• Verification

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