2 Instruction Memory

Mario Romero edited this page 2023-08-07 19:20:19 +00:00

Table of Contents

• Instruction Memory

Instruction Memory

Defined in rtl/instr_memory.sv

Figure	Direction	Signal
	Interface	instr_mem_if

The instruction memory is read only and the data can be specified using the FILE_PATH parameter. The file to read needs to be in the hexadecimal format provided by the $readmemh function of the SystemVerilog standard. Binary executables can be transformed to the hexadecimal format using objcopy or more convenient using the rvscc_bin_to_verilog_mem_file CMake function from cmake/utils.cmake that is being used when building the test or the sandbox project.

TODO: Add re-programmable memory

Table of Contents

• General Architecture
  • Datapaths
    • Single-Cycle
    • 5-Stage Multi-Cycle
    • 5-Stage Pipelined
  • Datapath units
    • Instruction Memory
    • ALU
    • Extend
    • Register File
  • Interfaces
    • Instruction Memory Interface
    • Data Memory Interface
    • AXI4
• Verification

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