1 Architecture

Mario Romero edited this page 2023-03-31 20:55:12 +00:00

The different cores at RVSCC integrate diverse pipelines with interfaces to interact with custom instruction and data memory systems. TODO: insert imem;pipeline;dmem diagram

Table of Contents

• General Architecture
  • Datapaths
    • Single-Cycle
    • 5-Stage Multi-Cycle
    • 5-Stage Pipelined
  • Datapath units
    • Instruction Memory
    • ALU
    • Extend
    • Register File
  • Interfaces
    • Instruction Memory Interface
    • Data Memory Interface
    • AXI4
• Verification

Welcome to the Wiki.