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67 lines
1.8 KiB
Verilog
67 lines
1.8 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [31:0] narrow;
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reg [63:0] quad;
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reg [127:0] wide;
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integer cyc; initial cyc=0;
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reg [7:0] crc;
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reg [6:0] index;
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always @ (posedge clk) begin
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//$write("[%0t] cyc==%0d crc=%b n=%x\n",$time, cyc, crc, narrow);
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cyc <= cyc + 1;
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if (cyc==0) begin
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// Setup
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narrow <= 32'h0;
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quad <= 64'h0;
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wide <= 128'h0;
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crc <= 8'hed;
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index <= 7'h0;
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end
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else if (cyc<90) begin
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index <= index + 7'h2;
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crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
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// verilator lint_off WIDTH
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if (index < 9'd20) narrow[index +: 3] <= crc[2:0];
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if (index < 9'd60) quad [index +: 3] <= crc[2:0];
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if (index < 9'd120) wide [index +: 3] <= crc[2:0];
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//
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narrow[index[3:0]] <= ~narrow[index[3:0]];
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quad [~index[3:0]]<= ~quad [~index[3:0]];
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wide [~index[3:0]] <= ~wide [~index[3:0]];
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// verilator lint_on WIDTH
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end
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else if (cyc==90) begin
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wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6;
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wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6;
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wide[82 +: 4] <=4'h6;
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end
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else if (cyc==91) begin
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wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1;
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wide[41] <=1'b1; quad[41] <=1'b1;
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wide[81] <=1'b1;
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n",$time, cyc, crc, narrow, quad, wide);
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if (crc != 8'b01111001) $stop;
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if (narrow != 32'h001661c7) $stop;
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if (quad != 64'h16d49b6f64266039) $stop;
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if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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