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Convert repository to git from svn.

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- Change .cvsignore to .gitignore
- Remove Id metacomments
- Cleanup whitespace at end of lines
This commit is contained in:
Wilson Snyder 2008-06-09 21:25:10 -04:00
parent 056f72f27f
commit 52912c6329
658 changed files with 636 additions and 1187 deletions
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2
.cvsignore → .gitignore vendored
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@ -7,7 +7,7 @@
*.1
*.tmp
*.tex
Makefile
/Makefile
README
config.cache
config.status

2
Changes
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@ -1244,8 +1244,6 @@ of input ports exists for tracing.
**** First code written.
----------------------------------------------------------------------
$Id$
----------------------------------------------------------------------
This uses outline mode in Emacs. See C-h m [M-x describe-mode].

25
Makefile.in
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@ -1,24 +1,23 @@
# $Id$
#*****************************************************************************
# DESCRIPTION: Verilator top level: Makefile pre-configure version
#
# This file is part of Verilator.
#
#
# This file is part of Verilator.
#
# Author: Wilson Snyder <wsnyder@wsnyder.org>
#
#
# Code available from: http://www.veripool.org/verilator
#
#
#*****************************************************************************
#
#
# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
#
#
# Verilator is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
#****************************************************************************/
#
# make all to compile and build Verilator.
@ -38,7 +37,7 @@
# source and built the program without creating any other files,
# `make distclean' should leave only the files that were in the
# distribution.
#
#
# make maintainer-clean
# Delete everything from the current directory that can be
# reconstructed with this Makefile. This typically includes
@ -62,7 +61,7 @@ TEXI2DVI = texi2dvi
PERL = @PERL@
# Destination prefix for RPMs
DESTDIR =
DESTDIR =
#### Don't edit: You're much better using configure switches to set these
prefix = @prefix@
@ -101,7 +100,7 @@ DISTDEP = info Makefile
# Files to distribute.
DISTBIN = $(wildcard bin/verilator-*)
DISTFILES_INC = $(INFOS) .cvsignore COPYING *.in *.ac \
DISTFILES_INC = $(INFOS) .gitignore COPYING *.in *.ac \
Changes README TODO \
MANIFEST.SKIP \
bin/* \
@ -321,7 +320,7 @@ clean mostlyclean distclean maintainer-clean maintainer-copy::
done
clean mostlyclean distclean maintainer-clean::
rm -f $(SCRIPTS) *.tmp
rm -f $(SCRIPTS) *.tmp
rm -f *.aux *.cp *.cps *.dvi *.fn *.fns *.ky *.kys *.log
rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx
rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas

17
TODO
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@ -1,4 +1,3 @@
// $Id$
// DESCRIPTION: Verilator: List of To Do issues.
//
// Copyright 2004-2008 by Wilson Snyder. This program is free software; you can
@ -7,7 +6,7 @@
Features:
Finish 3.400 new ordering fixes
Finish 3.400 new ordering fixes
Latch optimizations {Need here}
Task I/Os connecting to non-simple variables.
Fix nested casez statements expanding into to huge C++. [JeanPaul Vanitegem]
@ -50,7 +49,7 @@ Testing:
Usability:
Better reporting of unopt problems, including what lines of code
Report more errors (all of them?) before exiting [Eugene Weber]
Report more errors (all of them?) before exiting [Eugene Weber]
Internal Code:
Eliminate the AstNUser* passed to all visitors; its only needed in V3Width,
@ -69,7 +68,7 @@ Performance:
Multithreaded execution
Bit-multiply for faster bit swapping and a=b[1,3,2] random bit reorderings.
Move _last sets and all other combo logic inside master
if() that triggers on all possible sense items
if() that triggers on all possible sense items
Rewrite and combine V3Life, V3Subst
If block temp only ever set in one place to constant, propagate it
Used in t_mem for array delayed assignments
@ -139,15 +138,15 @@ Selectable SystemC types based on widths (see notes below)
c) a conditional whose possible values are (a) or (b)
2) One can lose that fact that a node is a tristate node. This happens
if a tristate node is assigned to a 'standard' node, or is used on
if a tristate node is assigned to a 'standard' node, or is used on
RHS of a conditional. The following infer tristate signals:
a) inout <SIGNAL>
b) tri <SIGNAL>
a) inout <SIGNAL>
b) tri <SIGNAL>
c) assigning to 'Z' (maybe through a conditional)
Note: tristate-ness of an output port determined only by
statements in the module (not the instances it calls)
4) Tristate variables can't be multidimensional arrays
5) Only check tristate contention between modules (not within!)
5) Only check tristate contention between modules (not within!)
6) Only simple compares with 'Z' are allowed (===)

4
bin/verilator
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@ -1,7 +1,6 @@
: # -*-Mode: perl;-*- use perl, wherever it is
eval 'exec perl -wS $0 ${1+"$@"}'
if 0;
# $Id$
######################################################################
#
# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
@ -84,7 +83,6 @@ run ($vcmd);
#----------------------------------------------------------------------
sub usage {
print '$Revision$$Date$ ', "\n";
pod2usage(-exitstatus=>2, -verbose=>2);
}
@ -915,7 +913,7 @@ example:
unsigned int main_time = 0; // Current simulation time
double sc_time_stamp () { // Called by $time in Verilog
return main_time;
return main_time;
}
int main() {

4
bin/verilator_difftree
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@ -1,7 +1,6 @@
: # -*-Mode: perl;-*- use perl, wherever it is
eval 'exec perl -wS $0 ${1+"$@"}'
if 0;
# $Id$
######################################################################
#
# Copyright 2005-2008 by Wilson Snyder <wsnyder@wsnyder.org>. This
@ -115,7 +114,6 @@ sub filter {
#----------------------------------------------------------------------
sub usage {
print '$Id$ ', "\n";
pod2usage(-verbose=>2, -exitval => 2);
exit (1);
}
@ -130,7 +128,7 @@ sub parameter {
$Opt_A = $param;
} elsif (!defined $Opt_B) {
$Opt_B = $param;
} else {
} else {
die "%Error: Unknown parameter: $param\n";
}
}

1
bin/verilator_includer
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@ -1,7 +1,6 @@
: # -*-Mode: perl;-*- use perl, wherever it is
eval 'exec perl -wS $0 ${1+"$@"}'
if 0;
# $Id$
# DESCRIPTION: Print include statements for each ARGV
#
# Copyright 2003-2008 by Wilson Snyder. This program is free software; you can

4
bin/verilator_profcfunc
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@ -1,7 +1,6 @@
: # -*-Mode: perl;-*- use perl, wherever it is
eval 'exec perl -wS $0 ${1+"$@"}'
if 0;
# $Id$
######################################################################
#
# Copyright 2007-2008 by Wilson Snyder <wsnyder@wsnyder.org>. This
@ -50,7 +49,6 @@ profcfunc($Opt_File);
#----------------------------------------------------------------------
sub usage {
print '$Id$ ', "\n";
pod2usage(-verbose=>2, -exitval => 2);
exit (1);
}
@ -63,7 +61,7 @@ sub parameter {
my $param = shift;
if (!defined $Opt_File) {
$Opt_File = $param;
} else {
} else {
die "%Error: Unknown parameter: $param\n";
}
}

2
configure.ac
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@ -1,10 +1,8 @@
dnl $Id$
dnl DESCRIPTION: Process this file with autoconf to produce a configure script.
dnl Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
dnl redistribute it and/or modify it under the terms of either the GNU
dnl General Public License or the Perl Artistic License.
AC_REVISION($Revision$)dnl
AC_INIT(src/Verilator.cpp)
AC_CONFIG_HEADER(src/config_build.h)

0
include/.cvsignore → include/.gitignore vendored
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12
include/verilated.cpp
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@ -1,4 +1,4 @@
// $Id$ -*- C++ -*-
// -*- C++ -*-
//*************************************************************************
//
// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
@ -9,7 +9,7 @@
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
//
//=========================================================================
///
/// \file
@ -86,7 +86,7 @@ IData VL_RAND_RESET_I(int outBits) {
if (Verilated::randReset()!=1) { // if 2, randomize
data = VL_RAND32();
}
if (outBits<32) data &= VL_MASK_I(outBits);
if (outBits<32) data &= VL_MASK_I(outBits);
return data;
}
@ -96,7 +96,7 @@ QData VL_RAND_RESET_Q(int outBits) {
if (Verilated::randReset()!=1) { // if 2, randomize
data = ((QData)VL_RAND32()<<VL_ULL(32)) | (QData)VL_RAND32();
}
if (outBits<64) data &= VL_MASK_Q(outBits);
if (outBits<64) data &= VL_MASK_Q(outBits);
return data;
}
@ -276,7 +276,7 @@ void VL_READMEM_W(bool hex, int width, int depth, int array_lsb, int fnwords,
else if (c=='\t' || c==' ' || c=='\r' || c=='\f') { if (innum) reading_addr=false; innum=false; }
// Skip // comments and detect /* comments
else if (ignore_to_cmt && lastc=='*' && c=='/') {
ignore_to_cmt = false; if (innum) reading_addr=false; innum=false;
ignore_to_cmt = false; if (innum) reading_addr=false; innum=false;
} else if (!ignore_to_eol && !ignore_to_cmt) {
if (lastc=='/' && c=='*') { ignore_to_cmt = true; }
else if (lastc=='/' && c=='/') { ignore_to_eol = true; }
@ -355,7 +355,7 @@ const char* Verilated::catName(const char* n1, const char* n2) {
// Used by symbol table creation to make module names
static char* strp = NULL;
static int len = -1;
int newlen = strlen(n1)+strlen(n2)+2;
int newlen = strlen(n1)+strlen(n2)+2;
if (newlen > len) {
if (strp) delete [] strp;
strp = new char[newlen];

42
include/verilated.h
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@ -1,4 +1,4 @@
// $Id$ -*- C++ -*-
// -*- C++ -*-
//*************************************************************************
//
// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
@ -9,7 +9,7 @@
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
//
//*************************************************************************
///
/// \file
@ -129,7 +129,7 @@ struct Verilated {
// Extern Vars
// Below two are used as bool, but having as uint32_t avoids conversion time
private:
static int s_randReset; ///< Random reset: 0=all 0s, 1=all 1s, 2=random
static int s_randReset; ///< Random reset: 0=all 0s, 1=all 1s, 2=random
static int s_debug; ///< See accessors... only when VL_DEBUG set
static bool s_calcUnusedSigs; ///< Waves file on, need all signals calculated
static bool s_gotFinish; ///< A $finish statement executed
@ -152,7 +152,7 @@ public:
#endif
/// Internal: Create a new module name by concatenating two strings
static const char* catName(const char* n1, const char* n2); // Returns new'ed data
/// Enable calculation of unused signals
/// Enable calculation of unused signals
static void calcUnusedSigs(bool flag) { s_calcUnusedSigs=flag; }
static bool calcUnusedSigs() { return s_calcUnusedSigs; } ///< Return calcUnusedSigs value
/// Did the simulation $finish?
@ -165,7 +165,7 @@ public:
/// Enable/disable assertions
static void assertOn(bool flag) { s_assertOn=flag; }
static bool assertOn() { return s_assertOn; }
};
};
//=========================================================================
// Extern functions -- User may override -- See verilated.cpp
@ -236,7 +236,7 @@ static inline QData VL_EXTENDSIGN_Q(int lbits, QData lhs) { return (-((lhs)&(VL
// Debugging prints
static inline void _VL_DEBUG_PRINT_W(int lbits, WDataInP iwp) {
printf(" Data: w%d: ", lbits);
printf(" Data: w%d: ", lbits);
for (int i=VL_WORDS_I(lbits)-1; i>=0; i--) { printf("%08x ",iwp[i]); }
printf("\n");
}
@ -878,7 +878,7 @@ static inline IData VL_POW_III(int, int, int rbits, IData lhs, IData rhs) {
return out;
}
#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs)
#define VL_POW_QQI(obits,lbits,rbits,lhs,rhs) VL_POW_QQQ(obits,lbits,rbits,lhs,rhs)
static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
if (lhs==0) return 0;
@ -896,23 +896,23 @@ static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) {
// INTERNAL: Stuff LHS bit 0++ into OUTPUT at specified offset
// ld may be "dirty", output is clean
static inline void _VL_INSERT_II(int, CData& lhsr, IData ld, int hbit, int lbit) {
static inline void _VL_INSERT_II(int, CData& lhsr, IData ld, int hbit, int lbit) {
IData insmask = (VL_MASK_I(hbit-lbit+1))<<lbit;
lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
}
static inline void _VL_INSERT_II(int, SData& lhsr, IData ld, int hbit, int lbit) {
static inline void _VL_INSERT_II(int, SData& lhsr, IData ld, int hbit, int lbit) {
IData insmask = (VL_MASK_I(hbit-lbit+1))<<lbit;
lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
}
static inline void _VL_INSERT_II(int, IData& lhsr, IData ld, int hbit, int lbit) {
static inline void _VL_INSERT_II(int, IData& lhsr, IData ld, int hbit, int lbit) {
IData insmask = (VL_MASK_I(hbit-lbit+1))<<lbit;
lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
}
static inline void _VL_INSERT_QQ(int, QData& lhsr, QData ld, int hbit, int lbit) {
static inline void _VL_INSERT_QQ(int, QData& lhsr, QData ld, int hbit, int lbit) {
QData insmask = (VL_MASK_Q(hbit-lbit+1))<<lbit;
lhsr = (lhsr & ~insmask) | ((ld<<lbit) & insmask);
}
static inline void _VL_INSERT_WI(int, WDataOutP owp, IData ld, int hbit, int lbit) {
static inline void _VL_INSERT_WI(int, WDataOutP owp, IData ld, int hbit, int lbit) {
int hoffset = VL_BITBIT_I(hbit);
int loffset = VL_BITBIT_I(lbit);
if (hoffset==VL_SIZEBITS_I && loffset==0) {
@ -937,7 +937,7 @@ static inline void _VL_INSERT_WI(int, WDataOutP owp, IData ld, int hbit, int lbi
// INTERNAL: Stuff large LHS bit 0++ into OUTPUT at specified offset
// lwp may be "dirty"
static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int lbit) {
static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int lbit) {
int hoffset = hbit & VL_SIZEBITS_I;
int loffset = lbit & VL_SIZEBITS_I;
int lword = VL_BITWORD_I(lbit);
@ -983,7 +983,7 @@ static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int
}
}
static inline void _VL_INSERT_WQ(int obits, WDataOutP owp, QData ld, int hbit, int lbit) {
static inline void _VL_INSERT_WQ(int obits, WDataOutP owp, QData ld, int hbit, int lbit) {
WData lwp[2]; VL_SET_WQ(lwp,ld);
_VL_INSERT_WW(obits,owp,lwp,hbit,lbit);
}
@ -1263,7 +1263,7 @@ static inline QData VL_SEL_QWII(int, int lbits, int, int, WDataInP lwp, IData ls
static inline WDataOutP VL_SEL_WWII(int obits,int lbits,int,int,WDataOutP owp,WDataInP lwp, IData lsb, IData width) {
int msb = lsb+width-1;
int word_shift = VL_BITWORD_I(lsb);
if (msb>lbits) { // Outside bounds,
if (msb>lbits) { // Outside bounds,
for (int i=0; i<VL_WORDS_I(obits)-1; i++) owp[i] = ~0;
owp[VL_WORDS_I(obits)-1] = VL_MASK_I(obits);
} else if (VL_BITBIT_I(lsb)==0) {
@ -1360,32 +1360,32 @@ static inline WDataOutP VL_CONST_W_3X(int obits, WDataOutP o,
o[0]=d0; o[1]=d1; o[2]=d2;
_END(obits,3); }
#define VL_HAVE_CONST_W_4X
static inline WDataOutP VL_CONST_W_4X(int obits, WDataOutP o,
static inline WDataOutP VL_CONST_W_4X(int obits, WDataOutP o,
I d3,I d2,I d1,I d0) {
o[0]=d0; o[1]=d1; o[2]=d2; o[3]=d3;
_END(obits,4); }
#define VL_HAVE_CONST_W_5X
static inline WDataOutP VL_CONST_W_5X(int obits, WDataOutP o,
static inline WDataOutP VL_CONST_W_5X(int obits, WDataOutP o,
I d4,I d3,I d2,I d1,I d0) {
o[0]=d0; o[1]=d1; o[2]=d2; o[3]=d3; o[4]=d4;
_END(obits,5); }
#define VL_HAVE_CONST_W_6X
static inline WDataOutP VL_CONST_W_6X(int obits, WDataOutP o,
static inline WDataOutP VL_CONST_W_6X(int obits, WDataOutP o,
I d5,I d4,I d3,I d2,I d1,I d0) {
o[0]=d0; o[1]=d1; o[2]=d2; o[3]=d3; o[4]=d4; o[5]=d5;
_END(obits,6); }
#define VL_HAVE_CONST_W_7X
static inline WDataOutP VL_CONST_W_7X(int obits, WDataOutP o,
static inline WDataOutP VL_CONST_W_7X(int obits, WDataOutP o,
I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
o[0]=d0; o[1]=d1; o[2]=d2; o[3]=d3; o[4]=d4; o[5]=d5; o[6]=d6;
_END(obits,7); }
#define VL_HAVE_CONST_W_8X
static inline WDataOutP VL_CONST_W_8X(int obits, WDataOutP o,
static inline WDataOutP VL_CONST_W_8X(int obits, WDataOutP o,
I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
o[0]=d0; o[1]=d1; o[2]=d2; o[3]=d3; o[4]=d4; o[5]=d5; o[6]=d6; o[7]=d7;
_END(obits,8); }
#define VL_HAVE_CONST_W_9X
static inline WDataOutP VL_CONST_W_9X(int obits, WDataOutP o,
static inline WDataOutP VL_CONST_W_9X(int obits, WDataOutP o,
I d8,
I d7,I d6,I d5,I d4,I d3,I d2,I d1,I d0) {
o[0]=d0; o[1]=d1; o[2]=d2; o[3]=d3; o[4]=d4; o[5]=d5; o[6]=d6; o[7]=d7;

8
include/verilated.mk.in
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@ -1,4 +1,4 @@
# $Id$ -*- Makefile -*-
# -*- Makefile -*-
######################################################################
# DESCRIPTION: Makefile commands for all verilated target files
#
@ -44,7 +44,7 @@ CPPFLAGS += -I. $(VK_CPPFLAGS_ALWAYS) $(VK_CPPFLAGS_WALL)
VPATH += ..
VPATH += $(VERILATOR_ROOT)/include
#OPT = -ggdb -DPRINTINITSTR -DDETECTCHANGE
#OPT = -ggdb -DPRINTINITSTR -DDETECTCHANGE
#OPT = -ggdb -DPRINTINITSTR
CPPFLAGS += $(OPT)
@ -59,11 +59,11 @@ LDFLAGS += $(USER_LDFLAGS)
# See the benchmarking section of bin/verilator.
# Support class optimizations. This includes the tracing and symbol table.
# SystemC takes minutes to optimize, thus it is off by default.
#OPT_SLOW =
#OPT_SLOW =
# Fast path optimizations. Most time is spent in these classes.
#OPT_FAST = -O2 -fstrict-aliasing
#OPT_FAST = -O
#OPT_FAST =
#OPT_FAST =
#######################################################################
##### Aggregates

6
include/verilated.v
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@ -1,4 +1,4 @@
// $Id$ -*- C++ -*-
// -*- C++ -*-
//*************************************************************************
//
// Code available from: http://www.veripool.org/verilator
@ -13,7 +13,7 @@
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
//
//=========================================================================
//
// DESCRIPTION: Verilator: Include in verilog files to hide verilator defines
@ -25,7 +25,7 @@
`ifdef verilator `else
`define coverage_block_off
`endif
// Hide file descriptor difference
`ifdef verilator
`define verilator_file_descriptor reg [63:0]

14
include/verilatedos.h
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@ -1,4 +1,4 @@
// $Id$ -*- C++ -*-
// -*- C++ -*-
//*************************************************************************
//
// Copyright 2003-2008 by Wilson Snyder. This program is free software; you can
@ -9,7 +9,7 @@
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
//
//*************************************************************************
///
/// \file
@ -84,7 +84,7 @@ typedef unsigned char vluint8_t; ///< 8-bit unsigned type
typedef unsigned short int vluint16_t; ///< 16-bit unsigned type
typedef long vlsint32_t; ///< 32-bit signed type
typedef unsigned long vluint32_t; ///< 32-bit unsigned type
typedef long long vlsint64_t; ///< 64-bit signed type
typedef long long vlsint64_t; ///< 64-bit signed type
typedef unsigned long long vluint64_t; ///< 64-bit unsigned type
#elif defined(_WIN32) && !defined(__MINGW32__)
typedef unsigned char uint8_t; ///< 8-bit unsigned type (backward compatibility)
@ -92,18 +92,18 @@ typedef unsigned short int uint16_t; ///< 16-bit unsigned type (backward co
typedef unsigned long uint32_t; ///< 32-bit unsigned type (backward compatibility)
typedef unsigned char vluint8_t; ///< 8-bit unsigned type
typedef unsigned short int vluint16_t; ///< 16-bit unsigned type
typedef int vlsint32_t; ///< 32-bit signed type
typedef int vlsint32_t; ///< 32-bit signed type
typedef unsigned int vluint32_t; ///< 32-bit unsigned type
typedef __int64 vlsint64_t; ///< 64-bit signed type
typedef __int64 vlsint64_t; ///< 64-bit signed type
typedef unsigned __int64 vluint64_t; ///< 64-bit unsigned type
#else // Linux or compliant Unix flavors, -m64
# include <stdint.h> // Linux and most flavors
# include <inttypes.h> // Solaris
typedef uint8_t vluint8_t; ///< 32-bit unsigned type
typedef uint16_t vluint16_t; ///< 32-bit unsigned type
typedef int vlsint32_t; ///< 32-bit signed type
typedef int vlsint32_t; ///< 32-bit signed type
typedef uint32_t vluint32_t; ///< 32-bit signed type
typedef long long vlsint64_t; ///< 64-bit signed type
typedef long long vlsint64_t; ///< 64-bit signed type
typedef unsigned long long vluint64_t; ///< 64-bit unsigned type
#endif

2
install-sh
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@ -115,7 +115,7 @@ fi
if [ x"$dir_arg" != x ]; then
dst=$src
src=""
if [ -d $dst ]; then
instcmd=:
else

2
mkinstalldirs
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@ -4,8 +4,6 @@
# Created: 1993-05-16
# Public domain
# $Id:$
errstatus=0
for file

7
nodist/bisonreader
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@ -1,5 +1,4 @@
#!/usr/bin/perl -w
#$Id$
######################################################################
#
# Copyright 2007-2008 by Wilson Snyder.
@ -7,16 +6,16 @@
# This program is free software; you can redistribute it and/or modify
# it under the terms of either the GNU General Public License or the
# Perl Artistic License.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the Perl Artistic License
# along with this module; see the file COPYING. If not, see
# www.cpan.org
#
#
######################################################################
# DESCRIPTION: Debugging of bison output

4
nodist/dot_importer
View File

@ -1,5 +1,4 @@
#!/usr/bin/perl -w
# $Id$
######################################################################
#
# Copyright 2005-2008 by Wilson Snyder <wsnyder@wsnyder.org>. This
@ -50,7 +49,6 @@ cwrite ("graph_export.cpp");
#----------------------------------------------------------------------
sub usage {
print '$Id$ ', "\n";
pod2usage(-verbose=>2, -exitval => 2);
exit (1);
}
@ -120,7 +118,7 @@ sub cwrite {
foreach my $edge (@Edges) {
$fh->printf(" new V3GraphEdge(gp, %s, %s, %s, %s);\n",
$edge->{from}, $edge->{to},
$edge->{weight}, $edge->{cutable}?"true":"false");
$edge->{weight}, $edge->{cutable}?"true":"false");
}
$fh->print("}\n");
}

4
nodist/dot_pruner
View File

@ -1,5 +1,4 @@
#!/usr/bin/perl -w
# $Id$
######################################################################
#
# Copyright 2005-2008 by Wilson Snyder <wsnyder@wsnyder.org>. This
@ -55,7 +54,6 @@ dotwrite();
#----------------------------------------------------------------------
sub usage {
print '$Id$ ', "\n";
pod2usage(-verbose=>2, -exitval => 2);
exit (1);
}
@ -175,7 +173,7 @@ __END__
=head1 NAME
dot_pruner -
dot_pruner -
=head1 SYNOPSIS

1
nodist/invoke_ncverilog
View File

@ -1,5 +1,4 @@
#!/usr/bin/perl -w
# $Id$
######################################################################
#
# Copyright 2007-2008 by Wilson Snyder <wsnyder@wsnyder.org>. This

4
nodist/leakchecking.txt Normal file
View File

@ -0,0 +1,4 @@
export GLIBCPP_FORCE_NEW=1
compile with -DVL_LEAK_CHECKS
valgrind --tool=memcheck --leak-check=yes /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg -MMD --bin /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg --cc -f /home/wsnyder/src/verilator/v4/verilator/test_c/../test_v/input.vc top.v --no-skip-identical 2>&1 | tee ~/d/aa
valgrind --tool=memcheck --leak-check=yes /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg -MMD --bin /home/wsnyder/src/verilator/v4/verilator/verilator_bin_dbg --cc /home/wsnyder/src/verilator/v4/verilator/test_regress/t/t_case_huge.v --no-skip-identical -I/home/wsnyder/src/verilator/v4/verilator/test_regress/t 2>&1 | tee ~/d/aa

6
nodist/vtree_importer
View File

@ -1,5 +1,4 @@
#!/usr/bin/perl -w
# $Id$
######################################################################
#
# Copyright 2005-2008 by Wilson Snyder <wsnyder@wsnyder.org>. This
@ -52,7 +51,6 @@ print '(query-replace-regexp "(\\([0-9a-z_]+\\))" "\\1" nil nil nil)',"\n";
#----------------------------------------------------------------------
sub usage {
print '$Id$ ', "\n";
pod2usage(-verbose=>2, -exitval => 2);
exit (1);
}
@ -292,7 +290,7 @@ sub p_var {
}
p "\t";
{
local $Avoid_Hex=1;
local $Avoid_Hex=1;
t1;
}
p "\t";
@ -322,7 +320,7 @@ __END__
=head1 NAME
vtree_importer -
vtree_importer -
=head1 SYNOPSIS

17
readme.texi
View File

@ -1,6 +1,5 @@
\input texinfo @c -*-texinfo-*-
@c %**start of header
$c $Id$
@setfilename readme.info
@settitle Verilator Installation
@c %**end of header
@ -15,13 +14,13 @@ $c $Id$
This is the Verilator Package.
@menu
* Copyright::
* Description::
* Obtaining Distribution::
* Directory Structure::
* Supported Systems::
* Installation::
* Limitations::
* Copyright::
* Description::
* Obtaining Distribution::
* Directory Structure::
* Supported Systems::
* Installation::
* Limitations::
@end menu
@node Copyright, Description, Top, Top
@ -56,7 +55,7 @@ The resulting executable will perform the actual simulation.
@node Obtaining Distribution, Directory Structure, Description, Top
@section Obtaining Distribution
The latest version is available at
The latest version is available at
@uref{http://www.veripool.org/verilator}
Download the latest package from that site, and decompress.

0
src/.cvsignore → src/.gitignore vendored
View File

6
src/Makefile.in
View File

@ -1,4 +1,4 @@
# $Id$ */
# -*- Makefile -*-
#*****************************************************************************
#
# DESCRIPTION: Verilator: Makefile for verilog source
@ -40,7 +40,7 @@ export OBJCACHE_HOSTS := $(shell rschedule --no-allow-reserved --similar hostnam
endif
ifeq ($(OBJCACHE_HOSTS),)
export OBJCACHE :=
export OBJCACHE :=
else
export OBJCACHE_JOBS := -j $(shell objcache --jobs "$(OBJCACHE_HOSTS)")
export OBJCACHE := @objcache --read --write
@ -74,7 +74,7 @@ prefiles::
ifeq ($(VERILATOR_AUTHOR_SITE),1) # Local... Else don't burden users
prefiles:: config_rev.h
# This output goes into srcdir, as we need to distribute it as part of the kit.
config_rev.h: config_rev.pl .svn/entries
config_rev.h: config_rev.pl ../.git/index
$(PERL) config_rev.pl . >$@
endif

2
src/Makefile_obj.in
View File

@ -1,4 +1,4 @@
# $Id$ -*- Makefile -*-
# -*- Makefile -*-
#*****************************************************************************
#
# DESCRIPTION: Verilator: Makefile for verilog source

3
src/V3Active.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Break always into sensitivity active domains
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Active's Transformations:
//
//
// Note this can be called multiple times.
// Create a IACTIVE(initial), SACTIVE(combo)
// ALWAYS: Remove any-edges from sense list

2
src/V3Active.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Break always into sensitivity block domains
//

3
src/V3ActiveTop.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Break always into sensitivity active domains
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Active's Transformations:
//
//
// Note this can be called multiple times.
// Across all ACTIVES
// SenTrees are now under each ACTIVE statement, we want them global:

2
src/V3ActiveTop.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Break always into sensitivity block domains
//

3
src/V3Assert.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Collect and print statistics
//
@ -106,7 +105,7 @@ private:
sentreep->unlinkFrBack();
//
AstNode* bodysp = NULL;
bool selfDestruct = false;
bool selfDestruct = false;
if (AstPslCover* snodep = nodep->castPslCover()) {
if (!v3Global.opt.coverageUser()) {
selfDestruct = true;

2
src/V3Assert.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Assertion expansion
//

1
src/V3AssertPre.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Collect and print statistics
//

2
src/V3AssertPre.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Assertion pre-expansion
//

17
src/V3Ast.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Ast node structures
//
@ -255,8 +254,8 @@ void AstNode::addNextHere(AstNode* newp) {
void AstNode::setOp1p(AstNode* newp) {
UASSERT(newp,"Null item passed to setOp1p\n");
UDEBUGONLY(if (m_op1p) this->v3fatalSrc("Adding to non-empty, non-list op1"););
UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op1"););
UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op1"););
this->debugTreeChange("-setOp1pThs: ", __LINE__, false);
newp->debugTreeChange("-setOp1pNew: ", __LINE__, true);
m_op1p = newp;
@ -268,8 +267,8 @@ void AstNode::setOp1p(AstNode* newp) {
void AstNode::setOp2p(AstNode* newp) {
UASSERT(newp,"Null item passed to setOp2p\n");
UDEBUGONLY(if (m_op2p) this->v3fatalSrc("Adding to non-empty, non-list op2"););
UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op2"););
UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op2"););
this->debugTreeChange("-setOp2pThs: ", __LINE__, false);
newp->debugTreeChange("-setOp2pNew: ", __LINE__, true);
m_op2p = newp;
@ -281,8 +280,8 @@ void AstNode::setOp2p(AstNode* newp) {
void AstNode::setOp3p(AstNode* newp) {
UASSERT(newp,"Null item passed to setOp3p\n");
UDEBUGONLY(if (m_op3p) this->v3fatalSrc("Adding to non-empty, non-list op3"););
UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op3"););
UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op3"););
this->debugTreeChange("-setOp3pThs: ", __LINE__, false);
newp->debugTreeChange("-setOp3pNew: ", __LINE__, true);
m_op3p = newp;
@ -294,8 +293,8 @@ void AstNode::setOp3p(AstNode* newp) {
void AstNode::setOp4p(AstNode* newp) {
UASSERT(newp,"Null item passed to setOp4p\n");
UDEBUGONLY(if (m_op4p) this->v3fatalSrc("Adding to non-empty, non-list op4"););
UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op4"););
UDEBUGONLY(if (newp->m_backp) newp->v3fatalSrc("Adding already linked node"););
UDEBUGONLY(if (newp->m_nextp) newp->v3fatalSrc("Adding list to non-list op4"););
this->debugTreeChange("-setOp4pThs: ", __LINE__, false);
newp->debugTreeChange("-setOp4pNew: ", __LINE__, true);
m_op4p = newp;

4
src/V3Ast.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Ast node structure
//
@ -1009,7 +1009,7 @@ public:
AstNodeFTaskRef(FileLine* fl, AstNode* namep, AstNode* pinsp)
:AstNode(fl)
, m_taskp(NULL) {
setOp1p(namep); addNOp2p(pinsp);
setOp1p(namep); addNOp2p(pinsp);
}
virtual ~AstNodeFTaskRef() {}
virtual bool broken() const { return m_taskp && !m_taskp->brokeExists(); }

1
src/V3AstNodes.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Ast node structures
//

10
src/V3AstNodes.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Ast node structure
//
@ -254,7 +254,7 @@ private:
m_sc=false; m_scClocked=false; m_scSensitive=false;
m_usedClock=false; m_usedParam=false;
m_sigPublic=false; m_sigModPublic=false;
m_funcLocal=false; m_funcReturn=false;
m_funcLocal=false; m_funcReturn=false;
m_attrClockEn=false; m_attrIsolateAssign=false;
m_fileDescr=false; m_isConst=false; m_isStatic=false;
m_trace=false;
@ -554,7 +554,7 @@ public:
virtual AstNode* clone() { return new AstVarXRef(*this);}
virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
virtual void dump(ostream& str);
string dotted() const { return m_dotted; }
string dotted() const { return m_dotted; }
string prettyDotted() const { return prettyName(dotted()); }
string inlinedDots() const { return m_inlinedDots; }
void inlinedDots(const string& flag) { m_inlinedDots = flag; }
@ -755,7 +755,7 @@ public:
AstNode* stmtsp() const { return op1p()->castNode(); } // op1 = List of statements
void addStmtp(AstNode* nodep) { addOp1p(nodep); }
};
struct AstGenerate : public AstNode {
// A Generate/end block
// Parents: MODULE
@ -1117,7 +1117,7 @@ private:
public:
AstCoverDecl(FileLine* fl, int column, const string& type, const string& comment)
: AstNodeStmt(fl) {
m_text = comment; m_typeText = type; m_column = column;
m_text = comment; m_typeText = type; m_column = column;
}
virtual ~AstCoverDecl() {}
virtual AstType type() const { return AstType::COVERDECL;}

3
src/V3Begin.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Removal of named begin blocks
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Begin's Transformations:
//
//
// Each module:
// Look for BEGINs
// BEGIN(VAR...) -> VAR ... {renamed}

2
src/V3Begin.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Removal of named begin blocks
//

1
src/V3Branch.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Branch prediction
//

2
src/V3Branch.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Branch prediction
//

3
src/V3Broken.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Find broken links in tree
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Broken's Transformations:
//
//
// Entire netlist
// Mark all nodes
// Check all links point to marked nodes

2
src/V3Broken.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Find broken links in tree
//

9
src/V3Case.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Break case statements up and add Unknown assigns
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Case's Transformations:
//
//
// Each module:
// TBD: Eliminate tristates by adding __in, __inen, __en wires in parallel
// Need __en in changed list if a signal is on the LHS of a assign
@ -235,7 +234,7 @@ private:
// new AstConst(cexprp->fileline(), nummask));
AstNode* and1p = new AstSel(cexprp->fileline(), cexprp->cloneTree(false),
msb, 1);
AstNode* eqp = new AstNeq(cexprp->fileline(),
AstNode* eqp = new AstNeq(cexprp->fileline(),
new AstConst(cexprp->fileline(), 0),
and1p);
AstIf* ifp = new AstIf(cexprp->fileline(), eqp, tree1p, tree0p);
@ -293,7 +292,7 @@ private:
for (AstNode* icondp = itemp->condsp(); icondp!=NULL; icondp=icondNextp) {
icondNextp = icondp->nextp();
icondp->unlinkFrBack();
AstNode* and1p;
AstNode* and2p;
AstConst* iconstp = icondp->castConst();
@ -305,7 +304,7 @@ private:
numval.opBitsOne(iconstp->num());
and1p = new AstAnd(itemp->fileline(), cexprp->cloneTree(false),
new AstConst(itemp->fileline(), nummask));
and2p = new AstAnd(itemp->fileline(),
and2p = new AstAnd(itemp->fileline(),
new AstConst(itemp->fileline(), numval),
new AstConst(itemp->fileline(), nummask));
icondp->deleteTree(); icondp=NULL; iconstp=NULL;

2
src/V3Case.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Break case statements up and add Unknown assigns
//

5
src/V3Cast.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Add C++ casts across expression size changes
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Cast's Transformations:
//
//
// Each module:
// For each math operator, if above operator requires 32 bits,
// and this isn't, cast to 32 bits.
@ -148,7 +147,7 @@ private:
&& nodep->backp()->width()
&& castSize(nodep) != castSize(nodep->varp())) {
// Cast vars to IData first, else below has upper bits wrongly set
// CData x=3; out = (QData)(x<<30);
// CData x=3; out = (QData)(x<<30);
insertCast (nodep, castSize(nodep));
}
nodep->user(1);

2
src/V3Cast.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Add C++ casts across expression size changes
//

3
src/V3Changed.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Add temporaries, such as for changed nodes
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Changed's Transformations:
//
//
// Each module:
// Each combo block
// For each variable that comes from combo block and is generated AFTER a usage

2
src/V3Changed.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Pre C-Emit stage changes
//

5
src/V3Clean.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Add temporaries, such as for clean nodes
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Clean's Transformations:
//
//
// Each module:
// For each math operator, if it requires a clean operand,
// and the operand is dirty, insert a CLEAN node.
@ -55,7 +54,7 @@ private:
// ENUMS
enum CleanState { UNKNOWN, CLEAN, DIRTY };
// METHODS
// Width resetting
int cppWidth(AstNode* nodep) {

2
src/V3Clean.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Pre C-Emit stage changes
//

5
src/V3Clock.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Clock's Transformations:
//
//
// Top Scope:
// Check created ACTIVEs
// Compress adjacent ACTIVEs with same sensitivity list
@ -416,7 +415,7 @@ private:
new AstConst(fl, 1)));
preUntilp->addNext(new AstAssign(fl, new AstVarRef(fl, countVarp, true),
new AstConst(fl, 0)));
// Add stable variables & preinits
AstNode* setChglastp = NULL;
for (AstVarRef* varrefp = nodep->stablesp(); varrefp; varrefp=varrefp->nextp()->castVarRef()) {

2
src/V3Clock.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Clocking POS/NEGEDGE insertion
//

5
src/V3Combine.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Combine common code into functions
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Combine's Transformations:
//
//
// For every function that we spit out
// Examine code to find largest common blocks
// Hash each node depth first
@ -32,7 +31,7 @@
// Make new function
// Move common block to function
// Replace each common block ref with funccall
//
//
//*************************************************************************
#include "config_build.h"

2
src/V3Combine.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Combine common code into functions
//

11
src/V3Const.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Constant folding
//
@ -102,7 +101,7 @@ private:
bool m_wremove; // Inside scope, no assignw removal
bool m_warn; // Output warnings
bool m_cpp; // C++ conversions only
AstModule* m_modp; // Current module
AstModule* m_modp; // Current module
AstNode* m_scopep; // Current scope
//int debug() { return 9; }
@ -143,7 +142,7 @@ private:
}
bool operandIsTwo(AstNode* nodep) {
return (nodep->castConst()
&& nodep->width() <= VL_QUADSIZE
&& nodep->width() <= VL_QUADSIZE
&& nodep->castConst()->asQuad()==2);
}
bool operandIsTwostate(AstNode* nodep) {
@ -745,7 +744,7 @@ private:
// Recurse rather then calling node->iterate to prevent 2^n recursion!
if (operandConcatMove(abConcp)) moveConcat(abConcp);
bcConcp->deleteTree(); bcConcp=NULL;
} else {
} else {
AstConcat* abConcp = nodep->lhsp()->castConcat(); abConcp->unlinkFrBack();
AstNode* ap = abConcp->lhsp()->unlinkFrBack();
AstNode* bp = abConcp->rhsp()->unlinkFrBack();
@ -1017,7 +1016,7 @@ private:
&& nodep->ifsp() && nodep->elsesp()) {
UINFO(4,"IF(NOT {x}) => IF(x) swapped if/else"<<nodep<<endl);
AstNode* condp = nodep->condp()->castNot()->lhsp()->unlinkFrBackWithNext();
AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext();
AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext();
AstNode* elsesp = nodep->elsesp()->unlinkFrBackWithNext();
AstIf* ifp = new AstIf(nodep->fileline(), condp, elsesp, ifsp);
ifp->branchPred(nodep->branchPred().invert());
@ -1038,7 +1037,7 @@ private:
nodep->deleteTree(); nodep=NULL;
}
else if (0 // Disabled, as vpm assertions are faster without due to short-circuiting
&& operandIfIf(nodep)) {
&& operandIfIf(nodep)) {
UINFO(0,"IF({a}) IF({b}) => IF({a} && {b})"<<endl);
AstNodeIf* lowerIfp = nodep->ifsp()->castNodeIf();
AstNode* condp = nodep->condp()->unlinkFrBack();

2
src/V3Const.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Propagate constants across AST
//

5
src/V3Coverage.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Netlist (top level) functions
//
@ -53,7 +52,7 @@ private:
bool m_checkBlock; // Should this block get covered?
AstModule* m_modp; // Current module to add statement to
FileMap m_fileps; // Column counts for each fileline
//int debug() { return 9; }
// METHODS
@ -66,7 +65,7 @@ private:
column = (it->second)++;
}
AstCoverDecl* declp = new AstCoverDecl(fl, column, type, comment);
AstCoverDecl* declp = new AstCoverDecl(fl, column, type, comment);
m_modp->addStmtp(declp);
return new AstCoverInc(fl, declp);

2
src/V3Coverage.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Coverage modules/signals together
//

3
src/V3Dead.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Dead code elimination
//
@ -21,7 +20,7 @@
// DEAD TRANSFORMATIONS:
// Remove any unreferenced modules
// Remove any unreferenced variables
//
//
//*************************************************************************
#include "config_build.h"

2
src/V3Dead.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Dead branch elimination
//

13
src/V3Delayed.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Add temporaries, such as for delayed nodes
//
@ -19,9 +18,9 @@
//
//*************************************************************************
// V3Delayed's Transformations:
//
//
// Each module:
// Replace ASSIGNDLY var, exp
// Replace ASSIGNDLY var, exp
// With ASSIGNDLY newvar, exp
// At top of block: VAR newvar
// At bottom of block: ASSIGNW var newvar
@ -269,7 +268,7 @@ private:
AstAlwaysPost* finalp = varrefp->varScopep()->user4p()->castNode()->castAlwaysPost();
if (!finalp) {
finalp = new AstAlwaysPost(nodep->fileline(), NULL/*sens*/, NULL/*body*/);
UINFO(9," Created "<<finalp<<endl);
UINFO(9," Created "<<finalp<<endl);
m_activep->addStmtsp(finalp);
varrefp->varScopep()->user4p(finalp);
}
@ -284,7 +283,7 @@ private:
new AstVarRef(nodep->fileline(), setvscp, false),
NULL,
NULL);
UINFO(9," Created "<<postLogicp<<endl);
UINFO(9," Created "<<postLogicp<<endl);
finalp->addBodysp(postLogicp);
finalp->user5p(setvscp); // Remember IF's vset variable
finalp->user4p(postLogicp); // and the associated IF, as we may be able to reuse it
@ -347,7 +346,7 @@ private:
virtual void visit(AstVarRef* nodep, AstNUser*) {
if (!nodep->user2()) { // Not done yet
nodep->user2(true);
if (m_inDly && nodep->lvalue()) {
UINFO(4,"AssignDlyVar: "<<nodep<<endl);
markVarUsage(nodep->varp(), VU_DLY);
@ -401,7 +400,7 @@ private:
m_activep->sensesp());
newactp->addStmtsp(prep); // Add to FRONT of statements
newactp->addStmtsp(postp);
m_activep->addNext(newactp);
m_activep->addNext(newactp);
dlyvscp->user2p(newactp);
}
AstVarRef* newrefp = new AstVarRef(nodep->fileline(), dlyvscp, true);

2
src/V3Delayed.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Pre C-Emit stage changes
//

5
src/V3Depth.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Prevent very deep expressions
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Depth's Transformations:
//
//
// Each module:
// For each wide OP, assign a temporary variable.
// For each deep expression, assign expression to temporary.
@ -111,7 +110,7 @@ private:
// We have some operator defines that use 2 parens, so += 2.
m_depth += 2;
if (m_depth>m_maxdepth) m_maxdepth=m_depth;
nodep->iterateChildren(*this);
nodep->iterateChildren(*this);
m_depth -= 2;
if (m_stmtp

2
src/V3Depth.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Prevent very deep expressions
//

3
src/V3DepthBlock.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Prevent very deep expressions
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3DepthBlock's Transformations:
//
//
// Each module:
// For each deep block, create cfunc including that block.
//

2
src/V3DepthBlock.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Prevent very deep expressions
//

3
src/V3Descope.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Rename scope references to module-local references
//
@ -24,7 +23,7 @@
// Change varref name() to be relative to current module
// Remove varScopep()
// This allows for better V3Combine'ing.
//
//
//*************************************************************************
#include "config_build.h"

2
src/V3Descope.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Rename scope references to module-local references
//

15
src/V3EmitC.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Emit C++ for tree
//
@ -80,9 +79,9 @@ public:
// METHODS
void displayEmit(AstDisplay* nodep);
string displayFormat(AstNode* widthNode, string in,
string displayFormat(AstNode* widthNode, string in,
char fmtLetter, bool padZero, bool reallyString);
void displayArg(AstDisplay* dispp, AstNode** elistp, string fmt, char fmtLetter);
void displayArg(AstDisplay* dispp, AstNode** elistp, string fmt, char fmtLetter);
void emitVarDecl(AstVar* nodep, const string& prefixIfImp);
typedef enum {EVL_IO, EVL_SIG, EVL_TEMP, EVL_STATIC, EVL_ALL} EisWhich;
@ -212,7 +211,7 @@ public:
}
virtual void visit(AstCoverDecl* nodep, AstNUser*) {
puts("__vlCoverInsert("); // As Declared in emitCoverageDecl
puts("&__Vcoverage[");
puts("&__Vcoverage[");
puts(cvtToStr(m_coverIds.remap(nodep))); puts("]");
puts(", \""); puts(nodep->fileline()->filebasename()); puts("\"");
puts(", "); puts(cvtToStr(nodep->fileline()->lineno()));
@ -639,7 +638,7 @@ class EmitCImp : EmitCStmts {
puts(modClassName(m_modp)+"::"+nodep->name()
+"("+cFuncArgs(nodep)+") {\n");
puts("VL_DEBUG_IF(cout<<\" ");
puts("VL_DEBUG_IF(cout<<\" ");
for (int i=0;i<m_modp->level();i++) { puts(" "); }
puts(modClassName(m_modp)+"::"+nodep->name()
+"\"<<endl; );\n");
@ -1678,7 +1677,7 @@ void EmitCImp::main(AstModule* modp, bool slow, bool fast) {
}
emitImp (modp);
for (AstNode* nodep=modp->stmtsp(); nodep; nodep = nodep->nextp()) {
if (AstCFunc* funcp = nodep->castCFunc()) {
if (v3Global.opt.outputSplit() > 1 && splitSize()
@ -1739,7 +1738,7 @@ class EmitCTrace : EmitCStmts {
puts("if (!Verilated::calcUnusedSigs()) vl_fatal(__FILE__,__LINE__,__FILE__,\"Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.\");\n");
puts("t->traceInitThis (vlSymsp, vcdp, code);\n");
puts("}\n");
puts("void "+topClassName()+"::traceFull(SpTraceVcd* vcdp, void* userthis, uint32_t code) {\n");
puts("// Callback from vcd->dump()\n");
puts(topClassName()+"* t=("+topClassName()+"*)userthis;\n");
@ -1909,7 +1908,7 @@ class EmitCTrace : EmitCStmts {
}
virtual void visit(AstCoverInc* nodep, AstNUser*) {
}
public:
EmitCTrace(bool slow) {
m_funcp = NULL;

2
src/V3EmitC.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Emit C++ code for module tree
//

2
src/V3EmitCBase.h
View File

@ -1,4 +1,4 @@
// $Id$ -*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Emit C++ for tree
//

1
src/V3EmitCInlines.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Emit C++ for tree
//

3
src/V3EmitCSyms.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Emit C++ for tree
//
@ -68,7 +67,7 @@ class EmitCSyms : EmitCBaseVisitor {
virtual void visit(AstNetlist* nodep, AstNUser*) {
// Collect list of scopes
nodep->iterateChildren(*this);
// Sort m_scopes by scope name
sort(m_scopes.begin(), m_scopes.end(), CmpName());
// Output

1
src/V3EmitMk.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Emit Makefile
//

2
src/V3EmitMk.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Emit Makefile
//

1
src/V3EmitV.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Emit Verilog from tree
//

2
src/V3EmitV.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
//-*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Emit Verilog code for module tree
//

5
src/V3Error.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Error handling
//
@ -47,7 +46,7 @@ bool V3Error::s_pretendError[V3ErrorCode::MAX];
struct v3errorIniter {
v3errorIniter() { V3Error::init(); };
};
v3errorIniter v3errorInit;
v3errorIniter v3errorInit;
//######################################################################
// ErrorCode class functions
@ -203,7 +202,7 @@ void FileLine::deleteAllRemaining() {
while (1) {
FileLineCheckSet::iterator it=fileLineLeakChecks.begin();
if (it==fileLineLeakChecks.end()) break;
delete *it;
delete *it;
// Operator delete will remove the iterated object from the list.
// Eventually the list will be empty and terminate the loop.
}

2
src/V3Error.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Error handling
//

29
src/V3Expand.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Add temporaries, such as for expand nodes
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Expand's Transformations:
//
//
// Each module:
// Expand verilated.h macros into internal micro optimizations (RTL)
// this will enable later optimizations.
@ -168,7 +167,7 @@ private:
}
return newp;
}
AstNode* newSelBitWord(AstNode* lsbp, int wordAdder) {
// Return equation to get the VL_BITWORD of a constant or non-constant
if (lsbp->castConst()) {
@ -355,7 +354,7 @@ private:
AstNode* lowwordp = new AstWordSel (nodep->fromp()->fileline(),
nodep->fromp()->cloneTree(true),
newSelBitWord(nodep->lsbp(), 0));
if (nodep->isQuad() && !lowwordp->isQuad()) lowwordp = new AstCast(nodep->fileline(), lowwordp, nodep);
if (nodep->isQuad() && !lowwordp->isQuad()) lowwordp = new AstCast(nodep->fileline(), lowwordp, nodep);
AstNode* lowp = new AstShiftR (nodep->fileline(),
lowwordp,
newSelBitBit(nodep->lsbp()),
@ -368,7 +367,7 @@ private:
new AstWordSel (nodep->fromp()->fileline(),
nodep->fromp()->cloneTree(true),
newSelBitWord(nodep->lsbp(), 1));
if (nodep->isQuad() && !midwordp->isQuad()) midwordp = new AstCast(nodep->fileline(), midwordp, nodep);
if (nodep->isQuad() && !midwordp->isQuad()) midwordp = new AstCast(nodep->fileline(), midwordp, nodep);
// If we're selecting bit zero, then all 32 bits in word 1 get shifted << by 32 bits
// else we need to form the lower word, so we << by 31 or less
// nbitsfromlow <= (lsb==0) ? 64-bitbit(lsb) : 32-bitbit(lsb)
@ -406,7 +405,7 @@ private:
new AstWordSel (nodep->fromp()->fileline(),
nodep->fromp()->cloneTree(true),
newSelBitWord(nodep->lsbp(), 2));
if (nodep->isQuad() && !hiwordp->isQuad()) hiwordp = new AstCast(nodep->fileline(), hiwordp, nodep);
if (nodep->isQuad() && !hiwordp->isQuad()) hiwordp = new AstCast(nodep->fileline(), hiwordp, nodep);
AstNode* himayp =
new AstShiftL (nodep->fileline(),
hiwordp,
@ -434,7 +433,7 @@ private:
UINFO(8," SEL->SHIFT "<<nodep<<endl);
AstNode* fromp = nodep->fromp()->unlinkFrBack();
AstNode* lsbp = nodep->lsbp()->unlinkFrBack();
if (nodep->isQuad() && !fromp->isQuad()) fromp = new AstCast(nodep->fileline(), fromp, nodep);
if (nodep->isQuad() && !fromp->isQuad()) fromp = new AstCast(nodep->fileline(), fromp, nodep);
AstNode* newp = new AstShiftR (nodep->fileline(),
fromp,
dropCondBound(lsbp),
@ -504,7 +503,7 @@ private:
bool destwide = lhsp->fromp()->isWide();
bool ones = nodep->rhsp()->isAllOnesV();
if (lhsp->lsbp()->castConst()) {
// The code should work without this constant test, but it won't
// The code should work without this constant test, but it won't
// constify as nicely as we'd like.
AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
AstNode* destp = lhsp->fromp()->unlinkFrBack();
@ -592,7 +591,7 @@ private:
// For wide destp, we can either form a equation for every destination word,
// with the appropriate long equation of if it's being written or not.
// Or, we can use a LHS variable arraysel with non-constant index to set the vector.
// Doing the variable arraysel is better for globals and large arrays,
// Doing the variable arraysel is better for globals and large arrays,
// doing every word is better for temporaries and if we're setting most words
// since it may result in better substitution optimizations later.
// This results in so much code, we're better off leaving a function call.
@ -630,7 +629,7 @@ private:
//newp->dumpTree(cout,"- new: ");
insertBefore(nodep,newp);
return true;
}
}
}
}
@ -641,10 +640,10 @@ private:
} else {
UINFO(8," CONCAT "<<nodep<<endl);
AstNode* lhsp = nodep->lhsp()->unlinkFrBack();
AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
int rhsshift = rhsp->widthMin();
if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep);
if (nodep->isQuad() && !rhsp->isQuad()) rhsp = new AstCast(nodep->fileline(), rhsp, nodep);
if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep);
if (nodep->isQuad() && !rhsp->isQuad()) rhsp = new AstCast(nodep->fileline(), rhsp, nodep);
AstNode* newp = new AstOr (nodep->fileline(),
new AstShiftL (nodep->fileline(),
lhsp,
@ -657,7 +656,7 @@ private:
}
bool expandWide (AstNodeAssign* nodep, AstConcat* rhsp) {
UINFO(8," Wordize ASSIGN(CONCAT) "<<nodep<<endl);
// Lhs or Rhs may be word, long, or quad.
// Lhs or Rhs may be word, long, or quad.
// newAstWordSelClone nicely abstracts the difference.
int rhsshift = rhsp->rhsp()->widthMin();
// Sometimes doing the words backwards is preferrable.
@ -690,7 +689,7 @@ private:
AstConst* constp = nodep->rhsp()->castConst();
if (!constp) nodep->v3fatalSrc("Replication value isn't a constant. Checked earlier!");
uint32_t times = constp->asInt();
if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep);
if (nodep->isQuad() && !lhsp->isQuad()) lhsp = new AstCast(nodep->fileline(), lhsp, nodep);
newp = lhsp->cloneTree(true);
for (unsigned repnum=1; repnum<times; repnum++) {
int rhsshift = repnum*lhswidth;

2
src/V3Expand.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Expansion of wide operator macros to C operators
//

1
src/V3File.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: File stream wrapper that understands indentation
//

2
src/V3File.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: File stream wrapper that understands indentation
//

7
src/V3Gate.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Gate optimizations, such as wire elimination
//
@ -19,7 +18,7 @@
//
//*************************************************************************
// V3Gate's Transformations:
//
//
// Extract a graph of the *entire* netlist with cells expanded
// Perform constant optimization across the graph
// Create VARSCOPEs for any variables we can rip out
@ -170,7 +169,7 @@ private:
// V3Const cleans up any NOTs by flipping the edges for us
if (m_buffersOnly
&& !(nodep->rhsp()->castVarRef()
// Until NEW_ORDERING, avoid making non-clocked logic into clocked,
// Until NEW_ORDERING, avoid making non-clocked logic into clocked,
// as it slows down the verilator_sim_benchmark
|| (nodep->rhsp()->castNot()
&& nodep->rhsp()->castNot()->lhsp()->castVarRef()
@ -343,7 +342,7 @@ private:
UINFO(5," VARREF to "<<varscp<<endl);
// We use weight of one; if we ref the var more than once, when we simplify,
// the weight will increase
if (nodep->lvalue()) {
if (nodep->lvalue()) {
new V3GraphEdge(&m_graph, m_logicVertexp, varvertexp, 1);
} else {
new V3GraphEdge(&m_graph, varvertexp, m_logicVertexp, 1);

2
src/V3Gate.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Break always into sensitivity block domains
//

7
src/V3GenClk.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Generated Clock repairs
//
@ -21,7 +20,7 @@
// GENCLK TRANSFORMATIONS:
// Follow control-flow graph with assignments and var usages
// ASSIGNDLY to variable later used as clock requires change detect
//
//
//*************************************************************************
#include "config_build.h"
@ -93,7 +92,7 @@ private:
}
//----
virtual void visit(AstVarRef* nodep, AstNUser*) {
// Consumption/generation of a variable,
// Consumption/generation of a variable,
AstVarScope* vscp = nodep->varScopep();
if (!vscp) nodep->v3fatalSrc("Scope not assigned");
if (m_activep && !nodep->user3()) {
@ -172,7 +171,7 @@ private:
//----
virtual void visit(AstVarRef* nodep, AstNUser*) {
// Consumption/generation of a variable,
// Consumption/generation of a variable,
AstVarScope* vscp = nodep->varScopep();
if (!vscp) nodep->v3fatalSrc("Scope not assigned");
if (m_activep) {

2
src/V3GenClk.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
//-*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Generated Clock Repairs
//

2
src/V3Global.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Common headers
//

4
src/V3Graph.cpp
View File

@ -1,4 +1,4 @@
// $Id$
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Graph optimizations
//
@ -106,7 +106,7 @@ ostream& operator<<(ostream& os, V3GraphVertex* vertexp) {
//######################################################################
// Edges
V3GraphEdge::V3GraphEdge(V3Graph* graphp,
V3GraphEdge::V3GraphEdge(V3Graph* graphp,
V3GraphVertex* fromp, V3GraphVertex* top, int weight,
bool cutable) {
UASSERT(fromp, "Null from pointer\n");

4
src/V3Graph.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
//-*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Graph optimizations
//
@ -67,7 +67,7 @@ public:
virtual ~V3Graph();
static void debug(int level) { s_debug = level; }
virtual string dotRankDir() { return "TB"; } // rankdir for dot plotting
// METHODS
void clear(); // Empty it of all vertices/edges, as if making a new object

1
src/V3GraphAcyc.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Graph acyclic algorithm
//

3
src/V3GraphAlg.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Graph optimizations
//
@ -345,7 +344,7 @@ private:
if (m_done) return;
m_callTrace.reserve(currentRank+10); // Leave slop for speed
m_callTrace[currentRank++] = vertexp;
m_callTrace[currentRank++] = vertexp;
if (vertexp->user() == 1) {
for (unsigned i=0; i<currentRank; i++) {

2
src/V3GraphAlg.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Graph algorithm base class
//

17
src/V3GraphDfa.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Graph optimizations
//
@ -224,7 +223,7 @@ private:
}
}
}
void main() {
UINFO(5,"Dfa to Nfa conversion...\n");
// Vertex::color() begin: 1 indicates vertex on DFA graph, 0=NFA graph
@ -236,7 +235,7 @@ private:
// Find NFA start
DfaVertex* nfaStartp = graphp()->findStart();
// Create new DFA State (start state) from the NFA states
DfaVertex* dfaStartp = newDfaVertex(nfaStartp);
@ -267,7 +266,7 @@ private:
}
}
if (debug()>=6) m_graphp->dumpDotFilePrefixed("dfa_start");
insertDfaOrigins(dfaStartp);
insertDfaOrigins(dfaStartp);
int i=0;
UINFO(5,"Main state conversion...\n");
@ -293,7 +292,7 @@ private:
}
}
}
// Foreach input state (NFA inputs of this DFA state)
for (set<DfaInput>::const_iterator inIt=inputs.begin(); inIt!=inputs.end(); ++inIt) {
DfaInput input = *inIt;
@ -303,7 +302,7 @@ private:
// Find all states reachable for given input
DfaStates nfasWithInput;
findNfasWithInput(dfaStatep, input, nfasWithInput/*ref*/);
// nfasWithInput now maps to the DFA we want a transition to.
// Does a DFA already exist with this, and only this subset of NFA's?
DfaVertex* toDfaStatep = findDfaOrigins(nfasWithInput);
@ -317,7 +316,7 @@ private:
new DfaEdge (graphp(), toDfaStatep, *nfaIt, DfaEdge::NA());
if ((*nfaIt)->accepting()) toDfaStatep->accepting(true);
}
insertDfaOrigins(toDfaStatep);
insertDfaOrigins(toDfaStatep);
}
// Add input transition
new DfaEdge (graphp(), dfaStatep, toDfaStatep, input);
@ -375,7 +374,7 @@ private:
}
void optimize_accepting_out() {
// Delete outbound edges from accepting states
// Delete outbound edges from accepting states
// (As once we've accepted, we no longer care about anything else.)
for (V3GraphVertex* vertexp = m_graphp->verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
if (DfaVertex* vvertexp = dynamic_cast<DfaVertex*>(vertexp)) {
@ -496,7 +495,7 @@ void DfaGraph::dfaReduce() {
// 2. All vertexes except start/accept get edges to NEW accept for any
// non-existing case. Weedely we don't have a nice way of representing
// this so we just create a edge for each case and mark it "complemented."
//
//
// 3. Delete temp vertex (old accept/new reject) and related edges.
// The user's old accept is now the new accept. This is imporant as
// we want the virtual type of it to be intact.

6
src/V3GraphDfa.h
View File

@ -1,4 +1,4 @@
// $Id$ //-*- C++ -*-
// -*- C++ -*-
//*************************************************************************
// DESCRIPTION: Verilator: Graph automata base class
//
@ -46,7 +46,7 @@ class DfaEdge;
/// at the end of the transformations. (If we want the complement, we
/// call complement and the algorithm makes a REJECT state, then flips
/// accept and reject for you.)
///
///
/// Common transforms:
///
/// "*": DfaVertex(START) --> [epsilon] -->DfaVertex(ACCEPT)
@ -87,7 +87,7 @@ public:
// Vertex
class DfaVertex : public V3GraphVertex {
// Each DFA state is captured in this vertex.
// Each DFA state is captured in this vertex.
// Start and accepting are members, rather than the more intuitive
// subclasses, as subclassing them would make it harder to inherit from here.
bool m_start; // Start state

37
src/V3GraphTest.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Graph tests
//
@ -112,7 +111,7 @@ public:
new V3GraphEdge(gp, g1, q, 2, true);
new V3GraphEdge(gp, g2, q, 2, true);
new V3GraphEdge(gp, g3, q, 2, true);
gp->stronglyConnected(&V3GraphEdge::followAlwaysTrue);
dump();
@ -143,7 +142,7 @@ public:
new V3GraphEdge(gp, g1, a, 2, true);
new V3GraphEdge(gp, g2, a, 2, true);
new V3GraphEdge(gp, g3, a, 2, true);
gp->acyclic(&V3GraphEdge::followAlwaysTrue);
gp->order();
dump();
@ -157,7 +156,7 @@ public:
V3Graph* gp = &m_graph;
V3GraphTestVertex* clk = new V3GraphTestVarVertex(gp,"$clk");
V3GraphTestVertex* a = new V3GraphTestVarVertex(gp,"$a");
V3GraphTestVertex* a_dly = new V3GraphTestVarVertex(gp,"$a_dly");
V3GraphTestVertex* a_dlyblk= new V3GraphTestVarVertex(gp,"$a_dlyblk");
@ -166,13 +165,13 @@ public:
V3GraphTestVertex* b_dlyblk= new V3GraphTestVarVertex(gp,"$b_dlyblk");
V3GraphTestVertex* c = new V3GraphTestVarVertex(gp,"$c");
V3GraphTestVertex* i = new V3GraphTestVarVertex(gp,"$i");
V3GraphTestVertex* ap = new V3GraphTestVarVertex(gp,"$a_pre");
V3GraphTestVertex* bp = new V3GraphTestVarVertex(gp,"$b_pre");
V3GraphTestVertex* cp = new V3GraphTestVarVertex(gp,"$c_pre");
V3GraphTestVertex* n;
// Logical order between clk, and posedge blocks
// implemented by special CLK prod/cons?
// Required order between first x_DLY<=x_pre and final x<=x_DLY
@ -183,23 +182,23 @@ public:
// implemented by producer/consumer on a_dly signals
// Desired order between different _DLY blocks so we can elim temporaries
// implemented by cutable "pre" signal dependencies
n = new V3GraphTestVertex(gp,"*INPUTS*"); {
new V3GraphEdge(gp, n, clk, 2);
new V3GraphEdge(gp, n, i, 2);
}
V3GraphTestVertex* posedge = n = new V3GraphTestVertex(gp,"*posedge clk*"); {
new V3GraphEdge(gp, clk, n, 2);
}
// AssignPre's VarRefs on LHS: generate special BLK
// normal: VarRefs on LHS: generate normal
// underSBlock: VarRefs on RHS: consume 'pre' (required to save cutable tests)
n = new V3GraphTestVertex(gp,"a_dly<PRE=a"); {
new V3GraphEdge(gp, n, a_dlyblk, 2); // Block ordering
new V3GraphEdge(gp, n, a_dly, 2);
new V3GraphEdge(gp, n, a_dly, 2);
new V3GraphEdge(gp, ap, n, 2, true); // DESIRED delayed ordering (inp is required)
new V3GraphEdge(gp, posedge, n, 2);
}
@ -209,7 +208,7 @@ public:
new V3GraphEdge(gp, bp, n, 2, true); // DESIRED delayed ordering
new V3GraphEdge(gp, posedge, n, 2);
}
// AssignDly's VarRefs on LHS: consume special BLK
// normal: VarRefs on LHS: generate normal
// underSBlock: VarRefs on RHS: generate 'pre' signals (cutable)
@ -228,7 +227,7 @@ public:
new V3GraphEdge(gp, n, ap, 2); // DESIRED delayed usage
new V3GraphEdge(gp, posedge, n, 2);
}
// AssignPost's
// normal: VarRefs on LHS: generate normal
// underSBlock: VarRefs on RHS: consume normal
@ -242,11 +241,11 @@ public:
new V3GraphEdge(gp, b_dly, n, 3);
new V3GraphEdge(gp, posedge, n, 2);
}
// COMBO
// Inbound edges are always uncutable, because we must put combo logic after sequential
// Outbound are cutable, as we may need to evaluate multiple times
{
V3GraphTestVertex* n = new V3GraphTestVertex(gp,"c=a|b|i");
new V3GraphEdge(gp, n, c, 1, true);
@ -254,7 +253,7 @@ public:
new V3GraphEdge(gp, b, n, 1, false);
new V3GraphEdge(gp, i, n, 1, false);
}
gp->acyclic(&V3GraphEdge::followAlwaysTrue);
gp->order();
@ -288,7 +287,7 @@ public:
DfaTestVertex* sr = new DfaTestVertex(gp,"sR");
DfaTestVertex* sz = new DfaTestVertex(gp,"sZ");
DfaTestVertex* sac = new DfaTestVertex(gp,"*ACCEPT*"); sac->accepting(true);
AstNUser* L = AstNUser::fromInt(0xaa);
AstNUser* R = AstNUser::fromInt(0xbb);
AstNUser* Z = AstNUser::fromInt(0xcc);
@ -340,7 +339,7 @@ public:
#if 0
# include "graph_export.cpp"
#else
#else
void V3GraphTestImport::dotImport() {
}
#endif

5
src/V3Hashed.cpp
View File

@ -1,4 +1,3 @@
// $Id$
//*************************************************************************
// DESCRIPTION: Verilator: Hashed common code into functions
//
@ -19,11 +18,11 @@
//
//*************************************************************************
// V3Hashed's Transformations:
//
//
// Hash each node depth first
// Hash includes varp name and operator type, and constants
// Form lookup table based on hash of each statement w/ nodep and next nodep
//
//
//*************************************************************************
#include "config_build.h"

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