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51 lines
1.1 KiB
Verilog
51 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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outc_w30, outd_w73,
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// Inputs
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clk, ina_w1, inb_w61
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);
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input clk;
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input ina_w1;
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input [60:0] inb_w61;
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output [29:0] outc_w30;
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output [72:0] outd_w73;
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sub sub (
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// Outputs
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.outy_w92 (outc_w30), // .large => (small)
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.outz_w22 (outd_w73), // .small => (large)
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// Inputs
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.clk (clk),
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.inw_w31 (ina_w1), // .large <= (small)
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.inx_w11 (inb_w61) // .small <= (large)
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);
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endmodule
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module sub (/*AUTOARG*/
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// Outputs
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outy_w92, outz_w22,
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// Inputs
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clk, inw_w31, inx_w11
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);
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input clk;
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input [30:0] inw_w31;
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input [10:0] inx_w11;
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output reg [91:0] outy_w92 /*verilator public*/;
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output reg [21:0] outz_w22 /*verilator public*/;
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always @(posedge clk) begin
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outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00};
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outz_w22 <= {inx_w11[10:0],inx_w11[10:0]};
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end
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endmodule // regfile
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