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96 lines
3.0 KiB
Verilog
96 lines
3.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2006 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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reg out1;
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reg [4:0] out2;
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sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
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always @ (posedge clk) begin
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//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n",$time, cyc, crc, sum, out1,out2);
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
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if (cyc==0) begin
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// Setup
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crc <= 64'h00000000_00000097;
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sum <= 64'h0;
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end
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else if (cyc==90) begin
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if (sum !== 64'hf0afc2bfa78277c5) $stop;
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end
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else if (cyc==91) begin
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end
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else if (cyc==92) begin
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end
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else if (cyc==93) begin
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end
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else if (cyc==94) begin
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub (/*AUTOARG*/
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// Outputs
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out1, out2,
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// Inputs
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in
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);
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input [23:0] in;
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output reg out1;
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output reg [4:0] out2;
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always @* begin
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// Test empty cases
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casez (in[0])
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endcase
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casez (in)
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24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
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24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
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24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
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24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
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24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
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24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
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24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
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24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
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24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
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// Same pattern, but reversed to test we work OK.
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24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
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24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
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24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
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24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
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24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
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24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
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24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
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24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
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24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
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24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
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24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
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24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
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24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
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24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
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24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
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24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
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endcase
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end
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endmodule
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