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19 lines
372 B
Verilog
19 lines
372 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005-2007 by Wilson Snyder.
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module t (/*AUTOARG*/);
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parameter P = 32'b1000;
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generate
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case (P)
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32'b0: initial begin end
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32'b1xxx: initial begin end
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default: initial begin end
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endcase
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endgenerate
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endmodule
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