Commit Graph

2227 Commits

Author SHA1 Message Date
Wilson Snyder
b25b798dbe Merge branch 'master' into develop-v5 2022-07-04 13:20:03 -04:00
Geza Lore
383e384739 Remove always true cfg_with_threaded from test driver 2022-06-27 15:23:32 +01:00
Wilson Snyder
e7ca4a69e3 Merge branch 'master' into develop-v5 2022-06-19 15:22:09 -04:00
Todd Strader
47b650d821
Fix public unpacked input ports (#3465) 2022-06-15 07:41:59 -04:00
Geza Lore
0c2c097377 Add -fno-merge-cond-motion option
This disables code motion during V3MergeCond, for debugging.
2022-06-13 14:16:11 +01:00
Kamil Rakoczy
660d1059b0
With --no-decoration, remove output whitespace (#3460)
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2022-06-10 07:26:33 -04:00
Wilson Snyder
e7dc2de14b Fix BLKANDNBLK on $readmem/$writemem (#3379). 2022-06-04 12:43:18 -04:00
Wilson Snyder
e2525d8440 Tests: Fix racy tests for develop-v5. 2022-06-04 12:22:11 -04:00
Wilson Snyder
6769106881 Merge branch 'master' into develop-v5 2022-06-04 12:17:29 -04:00
Wilson Snyder
32100a3c91 Tests: Fix racy tests for develop-v5. 2022-06-04 12:17:04 -04:00
Wilson Snyder
0f324c8309 Merge branch 'master' into develop-v5 2022-06-04 11:59:49 -04:00
Wilson Snyder
67f7432dd7 Commentary (#3436). 2022-06-04 08:37:42 -04:00
Wilson Snyder
59dc2853e3 Support concat assignment to packed array (#3446). 2022-06-03 21:32:13 -04:00
Wilson Snyder
ada58465b2 Add -f<optimization> options to replace -O<letter> options (#3436). 2022-06-03 20:43:16 -04:00
Wilson Snyder
173f57c636 Changed --no-merge-const-pool to -fno-merge-const-pool (#3436). 2022-06-03 19:41:59 -04:00
Yutetsu TAKATSUKASA
d64f979f99
Fix BitOpTree optimization to consider polarity of frozen node (#3445) (#3459)
* Tests: add a test to another failing case of #3445

* Consider polarity as lsb in BitOpTree optimization.
2022-06-01 09:26:16 +09:00
Yutetsu TAKATSUKASA
26b7452178
Fix #3445 of BitOpTreeOpt (#3453)
* Tests: Check BitOpTree statistics in t_const_opt.

* Tests: Add a test to reproduce #3445

* Fix #3445. Don't forget LSB of frozen node in BitOpTreeOpt.

* Apply suggestions from code review

Co-authored-by: Geza Lore <gezalore@gmail.com>
2022-05-30 19:33:06 +09:00
Geza Lore
d45caca011 Remove legacy VCD tracing API
This has not been used by Verilator for a while, but was kept for
compatibility with some external code. Now removed.
2022-05-28 12:07:24 +01:00
Geza Lore
0722f47539
Improve V3MergeCond by reordering statements (#3125)
V3MergeCond merges consecutive conditional `_ = cond ? _ : _` and
`if (cond) ...` statements. This patch adds an analysis and ordering
phase that moves statements with identical conditions closer to each
other, in order to enable more merging opportunities. This in turn
eliminates a lot of repeated conditionals which reduced dynamic branch
count and branch misprediction rate. Observed 6.5% improvement on
multi-threaded large designs, at the cost of less than 2% increase in
Verilation speed.
2022-05-27 16:57:51 +01:00
Krzysztof Bieganski
d7a75dc026 Merge branch 'master' into develop-v5 2022-05-25 11:06:38 +02:00
Wilson Snyder
530817191e Support non-ANSI interface port declarations (#3439). 2022-05-25 00:50:50 -04:00
Geza Lore
1282548a1c Only consider definitions in t_flag_csplit 2022-05-20 18:02:00 +01:00
Krzysztof Bieganski
9edccfdffa
Initial support for intra-assignment timing controls, net delays (#3427)
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-05-17 19:19:44 +01:00
Geza Lore
1a056f6db9 Fix invalid conditional merging when starting at 'c = c ? a : b'
Fixes #3409.
2022-05-17 18:36:40 +01:00
Krzysztof Bieganski
0a91ddf38a
Tests: Better grep check in t_foreach (#3435)
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-05-17 09:20:59 -04:00
Krzysztof Bieganski
67bb2c640e
Tests: Rename t_timing_clkgen to t_timing_clkgen1 (#3430)
This is a pre-PR to #3363, which will introduce more clock gen tests.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-05-17 09:19:51 -04:00
Geza Lore
282887d9c6 Fix code coverage holes
Fixes #3422
2022-05-16 21:22:21 +01:00
Krzysztof Bieganski
ecaa07a72a
Rename AstTimingControl to AstEventControl (#3425)
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
2022-05-16 20:44:41 +01:00
Wilson Snyder
c3c46967dc Tests: Appease sanitizer (#3121). 2022-05-15 11:50:52 -04:00
Geza Lore
599d23697d
IEEE compliant scheduler (#3384)
This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278
2022-05-15 16:03:32 +01:00
Wilson Snyder
5aa12e9b51 Add assert when VerilatedContext is mis-deleted (#3121). 2022-05-15 10:51:03 -04:00
Wilson Snyder
3c4131d45d Fix 'with' operator with type casting (#3387). 2022-05-15 09:53:48 -04:00
Wilson Snyder
ae8d8ee1ac Fix crash with misuse of display. 2022-05-15 09:29:45 -04:00
Geza Lore
766fb56651 Merge branch 'master' into develop-v5 2022-05-14 10:30:45 +01:00
Wilson Snyder
38438b3373 Internals: Cleanup some defaults. No functional change. 2022-05-12 23:30:39 -04:00
Wilson Snyder
71dedccbbe Support compile time trace signal selection with tracing_on/off (#3323). 2022-05-12 22:28:08 -04:00
Geza Lore
bec4610e12 Merge branch 'master' into develop-v5 2022-05-08 15:50:50 +01:00
Kamil Rakoczy
9378259779
Fix UNOPTFLAT warning from initial static var (#3406)
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2022-05-06 10:24:03 +02:00
Wilson Snyder
3d762282b9 Fix hang with large case statement optimization (#3405). 2022-05-05 07:02:52 -04:00
Geza Lore
2ad0bcbba9 Merge branch 'master' into develop-v5 2022-05-01 16:49:42 +01:00
Wilson Snyder
915ceb2d04 Tests: Untabify tests. No functional change. 2022-05-01 10:10:00 -04:00
Geza Lore
88bb7cdca6 Merge branch 'master' into develop-v5 2022-04-29 17:14:11 +01:00
Geza Lore
49c90ecbce Issue consistent INITIALDLY/COMBDLY/BLKSEQ warnings
Some cases of warnings about the use of blocking and non-blocking
assignments in combinational vs sequential processes were suppressed in
a way that is inconsistent with the *actual* current execution model of
Verilator. Turning these back on to, well, warn the user that these might
cause unexpected results. V5 will clean these up, but until then err on
the side of caution.

Fixes #864.
2022-04-29 17:05:44 +01:00
Kamil Rakoczy
5de1c619c8
Fix foreach segmentation fault (#3400). 2022-04-28 06:11:31 -04:00
Yoda Lee
a6d678d41d
Fix hang in generate symbol references (#3391) (#3398) 2022-04-27 18:40:36 -04:00
Geza Lore
46de9460a6 Merge branch 'master' into develop-v5 2022-04-23 15:38:30 +01:00
Geza Lore
62337bb6ac Future proofing some tests. No functional change. 2022-04-23 15:12:52 +01:00
Geza Lore
0b74e9b354 Ensure topological ordering of module list.
At the end of V3Param, fix up the module list to be topologically
sorted. We need to do this at the end as a later instantiation of a
recursive module might instantiate an earlier specialization, which we
cannot know until we processed everything. The rest of the compiler
depends on the module list being topologically sorted.

Fixes #3393
2022-04-23 13:25:27 +01:00
Geza Lore
5f0e1fae7f Simplify and clarify reporting of enclosing instance
Rename AstNodeModule::hierName -> someInstanceName and explain that this
is only used for user messages.

Rename AstNode::locationStr -> instanceStr and simplify implementation.
In particular, do not report an instance if we can't find a reasonable
guess.
2022-04-22 23:38:23 +01:00
Wilson Snyder
7bfc1a00a7 Fix tracing interfaces inside interfaces (#3309). 2022-04-14 09:14:44 -04:00