Fix public unpacked input ports (#3465)

src/V3Inline.cpp

@@ -311,8 +311,8 @@ private:
                 // code will be emitted.
                 UINFO(9, "assign to public and unpacked: " << nodep << endl);
                 m_modp->addStmtp(
-                    new AstAssignW(flp, new AstVarRef(flp, exprvarrefp->varp(), VAccess::WRITE),
-                                   new AstVarRef(flp, nodep, VAccess::READ)));
+                    new AstAssignW{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
+                                   new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
             } else if (nodep->isIfaceRef()) {
                 m_modp->addStmtp(
                     new AstAssignVarScope(flp, new AstVarRef(flp, nodep, VAccess::WRITE),

test_regress/t/t_pub_unpacked_port.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Todd Strader. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(
+    vlt => 1,
+    );
+
+compile();
+execute();
+ok(1);
+1;

test_regress/t/t_pub_unpacked_port.v

@@ -0,0 +1,55 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2022 by Todd Strader.
+// SPDX-License-Identifier: CC0-1.0
+
+module sub (
+   output logic [31:0] sub_s1up_out[0:0] /* verilator public_flat_rw */,
+   input logic sub_clk,
+   input logic [31:0] sub_s1up_in[0:0] /* verilator public_flat_rw */
+   );
+
+   // Evaluate clock edges
+   always @(posedge sub_clk) begin
+      sub_s1up_out <= sub_s1up_in;
+   end
+
+endmodule
+
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc = 0;
+   logic   [31:0]     s1up_in[1];
+   logic   [31:0]     s1up_out[1];
+
+   sub the_sub (
+      .sub_s1up_in (s1up_in),
+      .sub_s1up_out (s1up_out),
+      .sub_clk (clk));
+
+   always_comb   s1up_in[0] = cyc;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+
+      if (cyc == 10) begin
+         if (s1up_out[0] != 9) begin
+             $display("%%Error: got %0d instead of 9", s1up_out);
+             $stop;
+         end
+         if (the_sub.sub_s1up_in[0] != 10) begin
+             $display("%%Error: the_sub.sub_s1up_in was %0d instead of 10", the_sub.sub_s1up_in[0]);
+             $stop;
+         end
+         $display("final cycle = %0d", cyc);
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule