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160f3ee4a7
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3303 Commits

Author SHA1 Message Date
Geza Lore
160f3ee4a7 Remove dead code, no functional change 2022-05-25 19:11:20 +01:00
Krzysztof Bieganski
d7a75dc026 Merge branch 'master' into develop-v5 2022-05-25 11:06:38 +02:00
github action
a372e010bd Apply 'make format' 2022-05-25 04:51:51 +00:00
Wilson Snyder
530817191e Support non-ANSI interface port declarations (#3439). 2022-05-25 00:50:50 -04:00
Geza Lore
c7610ed044 Fix FST tracing thread in CMake build 2022-05-20 17:04:46 +01:00
Geza Lore
b130a8cfeb Add -DVM_TRACE_VCD in model builds with Make with --trace 2022-05-20 16:44:38 +01:00
Geza Lore
551bd284dd Rename some internals related to multi-threaded tracing 
Rename the implementation internals of current multi-threaded tracing to
be "offload mode". No functional change, nor user interface change
intended.
 2022-05-20 16:44:35 +01:00
Krzysztof Bieganski
9edccfdffa
Initial support for intra-assignment timing controls, net delays (#3427) 
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 19:19:44 +01:00
Geza Lore
1a056f6db9 Fix invalid conditional merging when starting at 'c = c ? a : b' 
Fixes #3409.
 2022-05-17 18:36:40 +01:00
Krzysztof Bieganski
e018eb7bac
Support AstClass::repairCache() after V3Class (#3431) 
This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-17 09:22:43 -04:00
Geza Lore
282887d9c6 Fix code coverage holes 
Fixes #3422
 2022-05-16 21:22:21 +01:00
Krzysztof Bieganski
3f7a248ed4
Refactor some of the Begin handling to a separate function (#3426) 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-16 20:45:33 +01:00
Krzysztof Bieganski
ecaa07a72a
Rename AstTimingControl to AstEventControl (#3425) 
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
 2022-05-16 20:44:41 +01:00
Geza Lore
0e62cd11da Don't issue DEPRECATED for now no-op clock_enable attribute 
Fixes #3421
 2022-05-16 18:57:51 +01:00
Geza Lore
599d23697d
IEEE compliant scheduler (#3384) 
This is a major re-design of the way code is scheduled in Verilator,
with the goal of properly supporting the Active and NBA regions of the
SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4.

With this change, all internally generated clocks should simulate
correctly, and there should be no more need for the `clock_enable` and
`clocker` attributes for correctness in the absence of Verilator
generated library models (`--lib-create`).

Details of the new scheduling model and algorithm are provided in
docs/internals.rst.

Implements #3278
 2022-05-15 16:03:32 +01:00
Wilson Snyder
3c4131d45d Fix 'with' operator with type casting (#3387). 2022-05-15 09:53:48 -04:00
Wilson Snyder
ae8d8ee1ac Fix crash with misuse of display. 2022-05-15 09:29:45 -04:00
Geza Lore
89ec3d16dc Allow const nodes in VNRef 
No functional change.
 2022-05-15 13:30:07 +01:00
HungMingWu
560efb2c9e
Internals: Fix memory leak in V3FileLine (#3407) (#3408). No functional change intended. 2022-05-14 18:15:38 -04:00
Wilson Snyder
38438b3373 Internals: Cleanup some defaults. No functional change. 2022-05-12 23:30:39 -04:00
Wilson Snyder
71dedccbbe Support compile time trace signal selection with tracing_on/off (#3323). 2022-05-12 22:28:08 -04:00
Wilson Snyder
bdfdc737a0 Internals: Cleanup V3Config. No functional change intended. 2022-05-11 00:47:52 -04:00
Wilson Snyder
3d045c3aee Internals: Cleanup some verilog.y formatting. No functional change. 2022-05-09 00:37:51 -04:00
HungMingWu
9583f152ee
Fix compile error when enable VL_LEAK_CHECKS (#3411). 
Signed-off-by: HungMingWu <u9089000@gmail.com>
 2022-05-08 20:49:13 -04:00
Wilson Snyder
5b2755d28d Untabify verilog.y (#3412). No functional change. 2022-05-08 20:46:18 -04:00
Kamil Rakoczy
9378259779
Fix UNOPTFLAT warning from initial static var (#3406) 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2022-05-06 10:24:03 +02:00
Wilson Snyder
3d762282b9 Fix hang with large case statement optimization (#3405). 2022-05-05 07:02:52 -04:00
Geza Lore
a2792785fe Add V3GraphVertex::dotRank to add GraphViz ranks to graph dumps 
This is a simple debugging aid to allow constraining the graph layout
via GraphViz rank directives. Note this is not related in any way to the
vertex 'rank' attribute used by some of the graph algorithms.

No functional change.
 2022-05-02 10:27:26 +01:00
Geza Lore
49c90ecbce Issue consistent INITIALDLY/COMBDLY/BLKSEQ warnings 
Some cases of warnings about the use of blocking and non-blocking
assignments in combinational vs sequential processes were suppressed in
a way that is inconsistent with the *actual* current execution model of
Verilator. Turning these back on to, well, warn the user that these might
cause unexpected results. V5 will clean these up, but until then err on
the side of caution.

Fixes #864.
 2022-04-29 17:05:44 +01:00
Geza Lore
8395004d25 Add AstNode::exists and AstNode::forall predicates 2022-04-29 15:44:22 +01:00
Kamil Rakoczy
5de1c619c8
Fix foreach segmentation fault (#3400). 2022-04-28 06:11:31 -04:00
Yoda Lee
a6d678d41d
Fix hang in generate symbol references (#3391) (#3398) 2022-04-27 18:40:36 -04:00
Aliaksei Chapyzhenka
2b91d764b5
Added missing #include <memory> (#3392) 
Fixes #3390
 2022-04-23 20:11:46 +01:00
Geza Lore
9abab2c366 Add separate AstInitialStatic node for static initializers 
Static variable initializers run before initial blocks, so use an
explicitly different procedure type for them. This also enables us to
now raise errors for assignments to const variables in initial blocks.
 2022-04-23 15:12:49 +01:00
Geza Lore
b22e368b25 Add default parameters to some Ast nodes for convenience 
Also update usage to utilize. No functional change.
 2022-04-23 14:47:16 +01:00
Geza Lore
a9cd2998e5 Don't mangle run-time library method names. 2022-04-23 14:47:16 +01:00
Geza Lore
f1ea30f257 Use iterate*Const V3EmitV visitors. No functional change. 2022-04-23 14:47:12 +01:00
Geza Lore
0b74e9b354 Ensure topological ordering of module list. 
At the end of V3Param, fix up the module list to be topologically
sorted. We need to do this at the end as a later instantiation of a
recursive module might instantiate an earlier specialization, which we
cannot know until we processed everything. The rest of the compiler
depends on the module list being topologically sorted.

Fixes #3393
 2022-04-23 13:25:27 +01:00
Geza Lore
8189416d0c Partial cleanup of V3Param. No functional change. 2022-04-23 13:03:52 +01:00
Geza Lore
5f0e1fae7f Simplify and clarify reporting of enclosing instance 
Rename AstNodeModule::hierName -> someInstanceName and explain that this
is only used for user messages.

Rename AstNode::locationStr -> instanceStr and simplify implementation.
In particular, do not report an instance if we can't find a reasonable
guess.
 2022-04-22 23:38:23 +01:00
HungMingWu
880a9be3b1
Internal: Add C++20ish reverse_view for range loops. No functional change (#3388). 
Signed-off-by: HungMingWu <u9089000@gmail.com>
 2022-04-18 13:03:56 -04:00
Wilson Snyder
7bfc1a00a7 Fix tracing interfaces inside interfaces (#3309). 2022-04-14 09:14:44 -04:00
Julien Margetts
baff64a43d
Add VK_USER_OBJS dependency to --create-lib library (#3370) (#3382). 2022-04-12 07:04:31 -04:00
github action
b7f2bb0e80 Apply 'make format' 2022-04-12 10:54:48 +00:00
HungMingWu
08e0a397d3
Fix debugi-V3Param null pointer fault (#3380) (#3381) 
Signed-off-by: HungMingWu <u9089000@gmail.com>
 2022-04-12 06:53:52 -04:00
Wilson Snyder
5f333be947 Internals: Dump TraceDecl codes. 2022-04-10 19:40:27 -04:00
Wilson Snyder
f5f4e15ce2 Fix filenames with dots overwriting debug .vpp files (#3373). 2022-04-10 10:33:16 -04:00
Geza Lore
fbd568dc47 Prep for multiple AstExecGraph. No functional change. 2022-04-10 12:00:17 +01:00
Geza Lore
c79ea88576 Fix incorrect localization when encountering non-leaf functions. 
Fixes #3286.
 2022-04-09 20:30:39 +01:00
Wilson Snyder
9be4e7b576 Fix Bison 3.8.2 error (#3366). 2022-03-31 19:14:13 -04:00