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Convert bad tests to --lint-only

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@911 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2007-04-18 18:45:41 +00:00
parent 77261cce5b
commit ea8445d187
18 changed files with 38 additions and 21 deletions
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2
src/V3Options.cpp
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@ -575,7 +575,7 @@ V3Options::V3Options() {
m_exe = false;
m_ignc = false;
m_l2Name = true;
m_lintOnly = true;
m_lintOnly = false;
m_makeDepend = true;
m_makePhony = false;
m_outFormatOk = false;

26
src/Verilator.cpp
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@ -433,18 +433,20 @@ void process () {
v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("dead.tree"));
}
// Fix very deep expressions
// Mark evaluation functions as member functions, if needed.
V3Depth::depthAll(v3Global.rootp());
//v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("depth.tree"));
if (!v3Global.opt.lintOnly()) {
// Fix very deep expressions
// Mark evaluation functions as member functions, if needed.
V3Depth::depthAll(v3Global.rootp());
//v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("depth.tree"));
// Branch prediction
V3Branch::branchAll(v3Global.rootp());
// Branch prediction
V3Branch::branchAll(v3Global.rootp());
// Add C casts when longs need to become long-long and vice-versa
// Note depth may insert something needing a cast, so this must be last.
V3Cast::castAll(v3Global.rootp());
v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("cast.tree"));
// Add C casts when longs need to become long-long and vice-versa
// Note depth may insert something needing a cast, so this must be last.
V3Cast::castAll(v3Global.rootp());
v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("cast.tree"));
}
V3Error::abortIfErrors();
@ -488,8 +490,8 @@ int main(int argc, char** argv, char** env) {
if (v3Global.opt.coverage() && !v3Global.opt.systemPerl() && !v3Global.opt.lintOnly()) {
v3fatal("Unsupported: Coverage analysis requires --sp output.");
}
if (!v3Global.opt.outFormatOk() && !v3Global.opt.preprocOnly()) {
v3fatal("verilator: Need --cc, --sc, --sp or --E option");
if (!v3Global.opt.outFormatOk() && !v3Global.opt.preprocOnly() && !v3Global.opt.lintOnly()) {
v3fatal("verilator: Need --cc, --sc, --sp, --lint-only or --E option");
}
V3Error::abortIfErrors();

3
test_regress/t/t_case_default_bad.pl
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@ -1,6 +1,6 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id:$
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Error: t/t_case_default_bad.v:\d+: Multiple default statements in case statement.

1
test_regress/t/t_case_genx_bad.pl
View File

@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Error: t/t_case_genx_bad.v:\d+: Use of x/\? constant in generate case statement, \(no such thing as \'generate casez\'\)

1
test_regress/t/t_case_x_bad.pl
View File

@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Error: t/t_case_x_bad.v:\d+: Use of x/. constant in case statement, \(perhaps intended casex/casez\)

3
test_regress/t/t_display_bad.pl
View File

@ -1,6 +1,6 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id:$
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Error: t/t_display_bad.v:\d+: Missing arguments for \$display format

1
test_regress/t/t_flag_werror_bad1.pl
View File

@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
top_filename("t/t_flag_werror.v");
compile (
v_flags2 => ["--lint-only"],
fails=>$Last_Self->{v3},
expect=>
'%Warning-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST generates 6 bits.

1
test_regress/t/t_flag_werror_bad2.pl
View File

@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
top_filename("t/t_flag_werror.v");
compile (
v_flags2 => ["--lint-only"],
fails=>$Last_Self->{v3},
verilator_flags=> [qw(-sp -Werror-WIDTH)],
expect=>

1
test_regress/t/t_func_bad.pl
View File

@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Error: t/t_func_bad.v:\d+: Too few arguments in function call

2
test_regress/t/t_func_bad2.pl
View File

@ -1,6 +1,6 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id:$
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can

3
test_regress/t/t_func_bad_width.pl
View File

@ -1,6 +1,6 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id:$
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>$Last_Self->{v3},
expect=>
'%Warning-WIDTH: t/t_func_bad_width.v:\d+: Operator FUNCREF expects 40 bits on the Function Argument, but Function Argument.s VARREF generates 39 bits.

1
test_regress/t/t_gen_var_bad.pl
View File

@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'.*%Error: t/t_gen_var_bad.v:\d+: Non-genvar used in generate for: i

1
test_regress/t/t_inst_array_bad.pl
View File

@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Error: t/t_inst_array_bad.v:19: Port connection __pinNumber2 as part of a module instance array requires 1 or 8 bits, but connection\'s VARREF generates 9 bits.

3
test_regress/t/t_inst_overwide_bad.pl
View File

@ -1,6 +1,6 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id:$
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2004 by Wilson Snyder. This program is free software; you can
@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
top_filename("t/t_inst_overwide.v");
compile (
v_flags2 => ["--lint-only"],
make_top_shell=>0,
verilator_flags=> [qw(-sp)],
verilator_make_gcc=>0,

3
test_regress/t/t_pp_misdef_bad.pl
View File

@ -1,6 +1,6 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id:$
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Error: t/t_pp_misdef_bad.v:11: Define or directive not defined: `NOTDEF

3
test_regress/t/t_select_bad_range.pl
View File

@ -1,6 +1,6 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id:$
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>$Last_Self->{v3},
expect=>
'%Error: t/t_select_bad_range.v:\d+: Selection index out of range: 44:44 outside 43:0

1
test_regress/t/t_var_bad_hide.pl
View File

@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>$Last_Self->{v3},
expect=>
'%Warning-VARHIDDEN: t/t_var_bad_hide.v:\d+: Declaration of signal hides declaration in upper scope: top

3
test_regress/t/t_var_in_assign_bad.pl
View File

@ -1,6 +1,6 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id:$
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2005 by Wilson Snyder. This program is free software; you can
@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Error: t/t_var_in_assign_bad.v:\d+: Assigning to input variable: value