diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index fccaddc18..2f2cda186 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -575,7 +575,7 @@ V3Options::V3Options() {
     m_exe = false;
     m_ignc = false;
     m_l2Name = true;
-    m_lintOnly = true;
+    m_lintOnly = false;
     m_makeDepend = true;
     m_makePhony = false;
     m_outFormatOk = false;
diff --git a/src/Verilator.cpp b/src/Verilator.cpp
index db8075f13..fddcc97d5 100644
--- a/src/Verilator.cpp
+++ b/src/Verilator.cpp
@@ -433,18 +433,20 @@ void process () {
 	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("dead.tree"));
     }
 
-    // Fix very deep expressions
-    // Mark evaluation functions as member functions, if needed.
-    V3Depth::depthAll(v3Global.rootp());
-    //v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("depth.tree"));
+    if (!v3Global.opt.lintOnly()) {
+	// Fix very deep expressions
+	// Mark evaluation functions as member functions, if needed.
+	V3Depth::depthAll(v3Global.rootp());
+	//v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("depth.tree"));
 
-    // Branch prediction
-    V3Branch::branchAll(v3Global.rootp());
+	// Branch prediction
+	V3Branch::branchAll(v3Global.rootp());
 
-    // Add C casts when longs need to become long-long and vice-versa
-    // Note depth may insert something needing a cast, so this must be last.
-    V3Cast::castAll(v3Global.rootp());
-    v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("cast.tree"));
+	// Add C casts when longs need to become long-long and vice-versa
+	// Note depth may insert something needing a cast, so this must be last.
+	V3Cast::castAll(v3Global.rootp());
+	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("cast.tree"));	
+    }
 
     V3Error::abortIfErrors();
 
@@ -488,8 +490,8 @@ int main(int argc, char** argv, char** env) {
     if (v3Global.opt.coverage() && !v3Global.opt.systemPerl() && !v3Global.opt.lintOnly()) {
 	v3fatal("Unsupported: Coverage analysis requires --sp output.");
     }
-    if (!v3Global.opt.outFormatOk() && !v3Global.opt.preprocOnly()) {
-	v3fatal("verilator: Need --cc, --sc, --sp or --E option");
+    if (!v3Global.opt.outFormatOk() && !v3Global.opt.preprocOnly() && !v3Global.opt.lintOnly()) {
+	v3fatal("verilator: Need --cc, --sc, --sp, --lint-only or --E option");
     }
 
     V3Error::abortIfErrors();
diff --git a/test_regress/t/t_case_default_bad.pl b/test_regress/t/t_case_default_bad.pl
index f13c48bae..18098ccba 100755
--- a/test_regress/t/t_case_default_bad.pl
+++ b/test_regress/t/t_case_default_bad.pl
@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_case_default_bad.v:\d+: Multiple default statements in case statement.
diff --git a/test_regress/t/t_case_genx_bad.pl b/test_regress/t/t_case_genx_bad.pl
index cdb9a629a..fbf032ef0 100755
--- a/test_regress/t/t_case_genx_bad.pl
+++ b/test_regress/t/t_case_genx_bad.pl
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_case_genx_bad.v:\d+: Use of x/\? constant in generate case statement, \(no such thing as \'generate casez\'\)
diff --git a/test_regress/t/t_case_x_bad.pl b/test_regress/t/t_case_x_bad.pl
index 00c7d7a8c..916a147c7 100755
--- a/test_regress/t/t_case_x_bad.pl
+++ b/test_regress/t/t_case_x_bad.pl
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_case_x_bad.v:\d+: Use of x/. constant in case statement, \(perhaps intended casex/casez\)
diff --git a/test_regress/t/t_display_bad.pl b/test_regress/t/t_display_bad.pl
index e6c7b5549..59dda774c 100755
--- a/test_regress/t/t_display_bad.pl
+++ b/test_regress/t/t_display_bad.pl
@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_display_bad.v:\d+: Missing arguments for \$display format
diff --git a/test_regress/t/t_flag_werror_bad1.pl b/test_regress/t/t_flag_werror_bad1.pl
index 85c0c3fa4..2aeae5d19 100755
--- a/test_regress/t/t_flag_werror_bad1.pl
+++ b/test_regress/t/t_flag_werror_bad1.pl
@@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 top_filename("t/t_flag_werror.v");
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 expect=>
 '%Warning-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST generates 6 bits.
diff --git a/test_regress/t/t_flag_werror_bad2.pl b/test_regress/t/t_flag_werror_bad2.pl
index b0a8e80df..9312ec010 100755
--- a/test_regress/t/t_flag_werror_bad2.pl
+++ b/test_regress/t/t_flag_werror_bad2.pl
@@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 top_filename("t/t_flag_werror.v");
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 verilator_flags=> [qw(-sp -Werror-WIDTH)],
 	 expect=>
diff --git a/test_regress/t/t_func_bad.pl b/test_regress/t/t_func_bad.pl
index 5beba7834..2aef402f8 100755
--- a/test_regress/t/t_func_bad.pl
+++ b/test_regress/t/t_func_bad.pl
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_func_bad.v:\d+: Too few arguments in function call
diff --git a/test_regress/t/t_func_bad2.pl b/test_regress/t/t_func_bad2.pl
index 98b735806..0bb5677b0 100755
--- a/test_regress/t/t_func_bad2.pl
+++ b/test_regress/t/t_func_bad2.pl
@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
diff --git a/test_regress/t/t_func_bad_width.pl b/test_regress/t/t_func_bad_width.pl
index 2e950b630..cefa7f5f0 100755
--- a/test_regress/t/t_func_bad_width.pl
+++ b/test_regress/t/t_func_bad_width.pl
@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 expect=>
 '%Warning-WIDTH: t/t_func_bad_width.v:\d+: Operator FUNCREF expects 40 bits on the Function Argument, but Function Argument.s VARREF generates 39 bits.
diff --git a/test_regress/t/t_gen_var_bad.pl b/test_regress/t/t_gen_var_bad.pl
index 4c13281f4..0b0b4da7d 100755
--- a/test_regress/t/t_gen_var_bad.pl
+++ b/test_regress/t/t_gen_var_bad.pl
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '.*%Error: t/t_gen_var_bad.v:\d+: Non-genvar used in generate for: i
diff --git a/test_regress/t/t_inst_array_bad.pl b/test_regress/t/t_inst_array_bad.pl
index 2adfb715c..9678a99b7 100755
--- a/test_regress/t/t_inst_array_bad.pl
+++ b/test_regress/t/t_inst_array_bad.pl
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_inst_array_bad.v:19: Port connection __pinNumber2 as part of a module instance array  requires 1 or 8 bits, but connection\'s VARREF generates 9 bits.
diff --git a/test_regress/t/t_inst_overwide_bad.pl b/test_regress/t/t_inst_overwide_bad.pl
index b29928188..a649b858f 100755
--- a/test_regress/t/t_inst_overwide_bad.pl
+++ b/test_regress/t/t_inst_overwide_bad.pl
@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2004 by Wilson Snyder. This program is free software; you can
@@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 top_filename("t/t_inst_overwide.v");
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 make_top_shell=>0,
 	 verilator_flags=> [qw(-sp)],
 	 verilator_make_gcc=>0,
diff --git a/test_regress/t/t_pp_misdef_bad.pl b/test_regress/t/t_pp_misdef_bad.pl
index 8041bfb5e..dab274477 100755
--- a/test_regress/t/t_pp_misdef_bad.pl
+++ b/test_regress/t/t_pp_misdef_bad.pl
@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_pp_misdef_bad.v:11: Define or directive not defined: `NOTDEF
diff --git a/test_regress/t/t_select_bad_range.pl b/test_regress/t/t_select_bad_range.pl
index 00782c15b..34d7c1671 100755
--- a/test_regress/t/t_select_bad_range.pl
+++ b/test_regress/t/t_select_bad_range.pl
@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 expect=>
 '%Error: t/t_select_bad_range.v:\d+: Selection index out of range: 44:44 outside 43:0
diff --git a/test_regress/t/t_var_bad_hide.pl b/test_regress/t/t_var_bad_hide.pl
index 8c07ed5ae..d8d6b4d46 100755
--- a/test_regress/t/t_var_bad_hide.pl
+++ b/test_regress/t/t_var_bad_hide.pl
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 expect=>
 '%Warning-VARHIDDEN: t/t_var_bad_hide.v:\d+: Declaration of signal hides declaration in upper scope: top
diff --git a/test_regress/t/t_var_in_assign_bad.pl b/test_regress/t/t_var_in_assign_bad.pl
index aa1fab17c..12b622577 100755
--- a/test_regress/t/t_var_in_assign_bad.pl
+++ b/test_regress/t/t_var_in_assign_bad.pl
@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2005 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_var_in_assign_bad.v:\d+: Assigning to input variable: value