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* V3Common.cpp::makeVlToString: fix `VL_TOSTRING_W` statement generation to include width argument * fix contribution name * add testcase for long struct `VL_TO_STRING_W` bug
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@ -14,6 +14,7 @@ Ameya Vikram Singh
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Andreas Kuster
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Andreas Kuster
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Andrew Nolte
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Andrew Nolte
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Arkadiusz Kozdra
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Arkadiusz Kozdra
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Aylon Chaim Porat
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Cameron Kirk
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Cameron Kirk
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Chris Randall
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Chris Randall
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Chuxuan Wang
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Chuxuan Wang
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@ -82,11 +82,13 @@ static void makeVlToString(AstNodeUOrStructDType* nodep) {
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}
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}
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stmt += VIdProtect::protect(itemp->prettyName()) + ":\" + ";
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stmt += VIdProtect::protect(itemp->prettyName()) + ":\" + ";
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if (VN_IS(itemp->dtypep()->skipRefp(), BasicDType) && itemp->isWide()) {
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if (VN_IS(itemp->dtypep()->skipRefp(), BasicDType) && itemp->isWide()) {
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stmt += "VL_TO_STRING_W";
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stmt += "VL_TO_STRING_W(";
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stmt += cvtToStr(itemp->widthWords());
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stmt += ", ";
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} else {
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} else {
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stmt += "VL_TO_STRING";
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stmt += "VL_TO_STRING(";
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}
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}
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stmt += "(obj." + itemp->nameProtect() + ");\n";
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stmt += "obj." + itemp->nameProtect() + ");\n";
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funcp->addStmtsp(new AstCStmt{nodep->fileline(), stmt});
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funcp->addStmtsp(new AstCStmt{nodep->fileline(), stmt});
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}
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}
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funcp->addStmtsp(new AstCStmt{nodep->fileline(), "out += \"}\";\n"});
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funcp->addStmtsp(new AstCStmt{nodep->fileline(), "out += \"}\";\n"});
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16
test_regress/t/t_trace_wide_struct.pl
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16
test_regress/t/t_trace_wide_struct.pl
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@ -0,0 +1,16 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile (verilator_flags2 => ['--trace --trace-structs'],);
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ok(1);
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1;
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23
test_regress/t/t_trace_wide_struct.v
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23
test_regress/t/t_trace_wide_struct.v
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@ -0,0 +1,23 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2011 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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typedef struct {
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logic [64:0] long_signal;
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} mystruct_t;
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mystruct_t mystruct;
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initial begin
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$finish;
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end
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endmodule
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