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Fix hashes of instances of parameterized classes (#4182)
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@ -307,7 +307,7 @@ private:
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}
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void visit(AstNodeModule* nodep) override {
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m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, false, [=]() { //
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m_hash += nodep->origName();
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m_hash += nodep->name();
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});
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}
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void visit(AstNodePreSel* nodep) override {
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21
test_regress/t/t_class_param_typedef.pl
Executable file
21
test_regress/t/t_class_param_typedef.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2022 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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47
test_regress/t/t_class_param_typedef.v
Normal file
47
test_regress/t/t_class_param_typedef.v
Normal file
@ -0,0 +1,47 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Foo #(type T=int);
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typedef Foo#(T) this_type;
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function int get_x;
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return T::get_s_x();
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endfunction
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endclass
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class Bar #(type S=int);
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typedef Bar #(S) this_type;
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typedef Foo#(this_type) foo_type;
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function int get_x;
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foo_type f = new;
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return f.get_x();
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endfunction
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static function int get_s_x;
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return S::x;
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endfunction
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endclass
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class Cls1;
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static int x = 1;
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typedef Bar#(Cls1) type_id;
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endclass
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class Cls2;
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static int x = 2;
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typedef Bar#(Cls2) type_id;
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endclass
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module t;
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initial begin
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Cls1::type_id bar1 = new;
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Cls2::type_id bar2 = new;
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if (bar1.get_x() != 1) $stop;
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if (bar2.get_x() != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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