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Improve to throw UNSUPPORTED instead of syntax error on extend class arguments
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@ -7190,6 +7190,15 @@ classExtendsOne<classExtendsp>: // IEEE: part of class_declaration
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class_typeExtImpList
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{ $$ = new AstClassExtends{$1->fileline(), $1, GRAMMARP->m_inImplements};
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$<scp>$ = $<scp>1; }
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| class_typeExtImpList '(' list_of_argumentsE ')'
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{ $$ = new AstClassExtends{$1->fileline(), $1, GRAMMARP->m_inImplements};
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BBUNSUP($<fl>2, "Unsupported: 'extends' with class list_of_arguments");
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$<scp>$ = $<scp>1; }
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// // IEEE-2023: Added: yEXTENDS class_type '(' yDEFAULT ')'
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| class_typeExtImpList '(' yDEFAULT ')'
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{ $$ = new AstClassExtends{$1->fileline(), $1, GRAMMARP->m_inImplements};
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BBUNSUP($<fl>2, "Unsupported: 'extends' with 'default'");
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$<scp>$ = $<scp>1; }
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;
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classImplementsE<classExtendsp>: // IEEE: part of class_declaration
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8
test_regress/t/t_class_extends_arg.out
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8
test_regress/t/t_class_extends_arg.out
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@ -0,0 +1,8 @@
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%Error-UNSUPPORTED: t/t_class_extends_arg.v:14:25: Unsupported: 'extends' with 'default'
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14 | class Cls1 extends Base1(default);
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| ^
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_class_extends_arg.v:18:25: Unsupported: 'extends' with class list_of_arguments
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18 | class Cls5 extends Base1(5);
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| ^
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%Error: Exiting due to
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16
test_regress/t/t_class_extends_arg.py
Executable file
16
test_regress/t/t_class_extends_arg.py
Executable file
@ -0,0 +1,16 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('linter')
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test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
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test.passes()
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36
test_regress/t/t_class_extends_arg.v
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36
test_regress/t/t_class_extends_arg.v
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@ -0,0 +1,36 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Base1;
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int s = 2;
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function new(int def = 3);
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s = def;
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endfunction
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endclass
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class Cls1 extends Base1(default);
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// Gets new(int def)
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endclass
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class Cls5 extends Base1(5);
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// Gets new()
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls1 c1;
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Cls1 c5;
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c1 = new(57);
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if (c1.s !== 57) $stop;
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c5 = new;
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if (c5.s !== 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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