From c2dcca980eedb3f78cd60ff9532a7cf7c1ee93f7 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 13 Dec 2024 17:15:04 -0500 Subject: [PATCH] Improve to throw UNSUPPORTED instead of syntax error on extend class arguments --- src/verilog.y | 9 +++++++ test_regress/t/t_class_extends_arg.out | 8 ++++++ test_regress/t/t_class_extends_arg.py | 16 ++++++++++++ test_regress/t/t_class_extends_arg.v | 36 ++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) create mode 100644 test_regress/t/t_class_extends_arg.out create mode 100755 test_regress/t/t_class_extends_arg.py create mode 100644 test_regress/t/t_class_extends_arg.v diff --git a/src/verilog.y b/src/verilog.y index ac6b34010..62eaa4815 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -7190,6 +7190,15 @@ classExtendsOne: // IEEE: part of class_declaration class_typeExtImpList { $$ = new AstClassExtends{$1->fileline(), $1, GRAMMARP->m_inImplements}; $$ = $1; } + | class_typeExtImpList '(' list_of_argumentsE ')' + { $$ = new AstClassExtends{$1->fileline(), $1, GRAMMARP->m_inImplements}; + BBUNSUP($2, "Unsupported: 'extends' with class list_of_arguments"); + $$ = $1; } + // // IEEE-2023: Added: yEXTENDS class_type '(' yDEFAULT ')' + | class_typeExtImpList '(' yDEFAULT ')' + { $$ = new AstClassExtends{$1->fileline(), $1, GRAMMARP->m_inImplements}; + BBUNSUP($2, "Unsupported: 'extends' with 'default'"); + $$ = $1; } ; classImplementsE: // IEEE: part of class_declaration diff --git a/test_regress/t/t_class_extends_arg.out b/test_regress/t/t_class_extends_arg.out new file mode 100644 index 000000000..a1ec3e818 --- /dev/null +++ b/test_regress/t/t_class_extends_arg.out @@ -0,0 +1,8 @@ +%Error-UNSUPPORTED: t/t_class_extends_arg.v:14:25: Unsupported: 'extends' with 'default' + 14 | class Cls1 extends Base1(default); + | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_class_extends_arg.v:18:25: Unsupported: 'extends' with class list_of_arguments + 18 | class Cls5 extends Base1(5); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_class_extends_arg.py b/test_regress/t/t_class_extends_arg.py new file mode 100755 index 000000000..30c3d4f77 --- /dev/null +++ b/test_regress/t/t_class_extends_arg.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_class_extends_arg.v b/test_regress/t/t_class_extends_arg.v new file mode 100644 index 000000000..c32818463 --- /dev/null +++ b/test_regress/t/t_class_extends_arg.v @@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class Base1; + int s = 2; + function new(int def = 3); + s = def; + endfunction +endclass + +class Cls1 extends Base1(default); + // Gets new(int def) +endclass + +class Cls5 extends Base1(5); + // Gets new() +endclass + +module t (/*AUTOARG*/); + initial begin + Cls1 c1; + Cls1 c5; + c1 = new(57); + if (c1.s !== 57) $stop; + + c5 = new; + if (c5.s !== 5) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule