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37 lines
677 B
Systemverilog
37 lines
677 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Base1;
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int s = 2;
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function new(int def = 3);
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s = def;
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endfunction
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endclass
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class Cls1 extends Base1(default);
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// Gets new(int def)
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endclass
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class Cls5 extends Base1(5);
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// Gets new()
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endclass
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module t (/*AUTOARG*/);
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initial begin
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Cls1 c1;
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Cls1 c5;
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c1 = new(57);
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if (c1.s !== 57) $stop;
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c5 = new;
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if (c5.s !== 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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