Improve to throw UNSUPPORTED instead of syntax error on extend class arguments

This commit is contained in:
Wilson Snyder 2024-12-13 17:15:04 -05:00
parent a23dfdc4ee
commit c2dcca980e
4 changed files with 69 additions and 0 deletions

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@ -7190,6 +7190,15 @@ classExtendsOne<classExtendsp>: // IEEE: part of class_declaration
class_typeExtImpList class_typeExtImpList
{ $$ = new AstClassExtends{$1->fileline(), $1, GRAMMARP->m_inImplements}; { $$ = new AstClassExtends{$1->fileline(), $1, GRAMMARP->m_inImplements};
$<scp>$ = $<scp>1; } $<scp>$ = $<scp>1; }
| class_typeExtImpList '(' list_of_argumentsE ')'
{ $$ = new AstClassExtends{$1->fileline(), $1, GRAMMARP->m_inImplements};
BBUNSUP($<fl>2, "Unsupported: 'extends' with class list_of_arguments");
$<scp>$ = $<scp>1; }
// // IEEE-2023: Added: yEXTENDS class_type '(' yDEFAULT ')'
| class_typeExtImpList '(' yDEFAULT ')'
{ $$ = new AstClassExtends{$1->fileline(), $1, GRAMMARP->m_inImplements};
BBUNSUP($<fl>2, "Unsupported: 'extends' with 'default'");
$<scp>$ = $<scp>1; }
; ;
classImplementsE<classExtendsp>: // IEEE: part of class_declaration classImplementsE<classExtendsp>: // IEEE: part of class_declaration

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@ -0,0 +1,8 @@
%Error-UNSUPPORTED: t/t_class_extends_arg.v:14:25: Unsupported: 'extends' with 'default'
14 | class Cls1 extends Base1(default);
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_class_extends_arg.v:18:25: Unsupported: 'extends' with class list_of_arguments
18 | class Cls5 extends Base1(5);
| ^
%Error: Exiting due to

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@ -0,0 +1,16 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('linter')
test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
test.passes()

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@ -0,0 +1,36 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class Base1;
int s = 2;
function new(int def = 3);
s = def;
endfunction
endclass
class Cls1 extends Base1(default);
// Gets new(int def)
endclass
class Cls5 extends Base1(5);
// Gets new()
endclass
module t (/*AUTOARG*/);
initial begin
Cls1 c1;
Cls1 c5;
c1 = new(57);
if (c1.s !== 57) $stop;
c5 = new;
if (c5.s !== 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule