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Tests: Remove unused clk input

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This commit is contained in:
Wilson Snyder 2024-10-07 19:14:41 -04:00
parent 2c445e4bfd
commit bbce7926b9
64 changed files with 115 additions and 317 deletions
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6
test_regress/t/t_array_compare.v
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@ -6,11 +6,7 @@
// bug1071
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
reg [3:0] array_1 [2:0];
reg [3:0] array_2 [2:0];

6
test_regress/t/t_array_index_increment.v
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@ -4,11 +4,7 @@
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
string test_string = "abcd";

6
test_regress/t/t_array_type_methods.v
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@ -8,11 +8,7 @@
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
logic [3:0] foo [1:0];
logic [3:0] fooe [1:0];

4
test_regress/t/t_bitsel_const_bad.out
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@ -1,5 +1,5 @@
%Error: t/t_bitsel_const_bad.v:21:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic'
%Error: t/t_bitsel_const_bad.v:16:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic'
: ... note: In instance 't'
21 | assign a = b[0];
16 | assign a = b[0];
| ^
%Error: Exiting due to

7
test_regress/t/t_bitsel_const_bad.v
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@ -6,12 +6,7 @@
// without warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
// Note that if we declare "wire [0:0] b", this works just fine.
wire a;

6
test_regress/t/t_bitsel_struct.v
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@ -9,12 +9,8 @@
// without warranty, 2012 by Jie Xu.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
module t(/*AUTOARG*/);
input clk;
typedef struct packed {
logic [1:0][15:0] channel;
logic others;

6
test_regress/t/t_bitsel_struct3.v
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@ -12,12 +12,8 @@
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t(/*AUTOARG*/
// Inputs
clk
);
module t(/*AUTOARG*/);
input clk;
typedef struct packed {
logic [15:0] channel;
logic [15:0] others;

4
test_regress/t/t_bitsel_wire_array_bad.out
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@ -1,5 +1,5 @@
%Error: t/t_bitsel_wire_array_bad.v:21:16: Illegal assignment of constant to unpacked array
%Error: t/t_bitsel_wire_array_bad.v:16:16: Illegal assignment of constant to unpacked array
: ... note: In instance 't'
21 | assign b = a[0];
16 | assign b = a[0];
| ^
%Error: Exiting due to

7
test_regress/t/t_bitsel_wire_array_bad.v
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@ -6,12 +6,7 @@
// without warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
// a and b are arrays of length 1.
wire a[0:0]; // Array of nets

7
test_regress/t/t_class_static.v
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@ -30,12 +30,7 @@ class Cls;
endfunction
endclass
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
Cls a = new;
Cls b = new;

7
test_regress/t/t_class_static_member.v
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@ -25,12 +25,7 @@ class Cls;
endclass
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
Cls a = new;
Cls b = new;

7
test_regress/t/t_class_static_member_pkg.v
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@ -27,12 +27,7 @@ class Cls;
endclass
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
Pkg::Cls a = new;
Pkg::Cls b = new;

4
test_regress/t/t_class_super_bad.out
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@ -1,4 +1,4 @@
%Error: t/t_class_super_bad.v:15:12: 'super' used outside class (IEEE 1800-2023 8.15)
15 | super.addr = 2;
%Error: t/t_class_super_bad.v:12:12: 'super' used outside class (IEEE 1800-2023 8.15)
12 | super.addr = 2;
| ^
%Error: Exiting due to

7
test_regress/t/t_class_super_bad.v
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@ -5,11 +5,8 @@
// SPDX-License-Identifier: CC0-1.0
//
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
module t(/*AUTOARG*/);
bit [3:0] addr;
initial begin
super.addr = 2;

7
test_regress/t/t_class_uses_this.v
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@ -41,11 +41,8 @@ class wrapped_int;
endfunction
endclass
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
module t(/*AUTOARG*/);
Cls bar;
Cls baz;
wrapped_int i1, i2;

4
test_regress/t/t_class_uses_this_bad.out
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@ -1,4 +1,4 @@
%Error: t/t_class_uses_this_bad.v:15:12: 'this' used outside class (IEEE 1800-2023 8.11)
15 | this.addr = 2;
%Error: t/t_class_uses_this_bad.v:11:12: 'this' used outside class (IEEE 1800-2023 8.11)
11 | this.addr = 2;
| ^
%Error: Exiting due to

6
test_regress/t/t_class_uses_this_bad.v
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@ -5,11 +5,7 @@
// SPDX-License-Identifier: CC0-1.0
//
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
module t(/*AUTOARG*/);
bit [3:0] addr;
initial begin
this.addr = 2;

6
test_regress/t/t_class_vparam.v
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@ -22,11 +22,7 @@ class arg_class_t;
int ifield;
endclass
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
vclass vir;
paramed_class_t#(arg_class_t) argu;

6
test_regress/t/t_enum_size.v
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@ -4,11 +4,7 @@
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
// verilator lint_off WIDTH
typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs;

7
test_regress/t/t_flag_parameter_pkg.v
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@ -9,12 +9,7 @@ package pack_a;
endpackage : pack_a
//module t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
parameter PARAM_A = 0;

16
test_regress/t/t_func_no_lifetime_bad.out
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@ -1,19 +1,19 @@
%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:29:17: Function/task's lifetime implicitly set to static
%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:26:17: Function/task's lifetime implicitly set to static
: ... Suggest use 'function automatic' or 'function static'
29 | function int f_implicit_static();
26 | function int f_implicit_static();
| ^~~~~~~~~~~~~~~~~
t/t_func_no_lifetime_bad.v:30:11: ... Location of implicit static variable
30 | int cnt = 0;
t/t_func_no_lifetime_bad.v:27:11: ... Location of implicit static variable
27 | int cnt = 0;
| ^~~
... Suggest use 'function automatic' or 'function static'
... For warning description see https://verilator.org/warn/IMPLICITSTATIC?v=latest
... Use "/* verilator lint_off IMPLICITSTATIC */" and lint_on around source to disable this message.
%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:34:9: Function/task's lifetime implicitly set to static
%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:31:9: Function/task's lifetime implicitly set to static
: ... Suggest use 'function automatic' or 'function static'
34 | task t_implicit_static();
31 | task t_implicit_static();
| ^~~~~~~~~~~~~~~~~
t/t_func_no_lifetime_bad.v:35:11: ... Location of implicit static variable
35 | int cnt = 0;
t/t_func_no_lifetime_bad.v:32:11: ... Location of implicit static variable
32 | int cnt = 0;
| ^~~
... Suggest use 'function automatic' or 'function static'
%Warning-IMPLICITSTATIC: t/t_func_no_lifetime_bad.v:9:8: Variable's lifetime implicitly set to static

7
test_regress/t/t_func_no_lifetime_bad.v
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@ -21,10 +21,7 @@ task t_dunit_static_ok(input int in_ok = 1);
$display("%d", ++cnt_ok);
endtask
module t (/*AUTOARG*/
// Inputs
clk
);
module t (/*AUTOARG*/);
function int f_implicit_static();
int cnt = 0;
@ -42,8 +39,6 @@ module t (/*AUTOARG*/
return ++cnt;
endfunction
input clk;
int a, b;
initial begin
a = f_dunit_static();

4
test_regress/t/t_func_no_parentheses_bad.out
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@ -1,4 +1,4 @@
%Error: t/t_func_no_parentheses_bad.v:21:11: Found definition of 'func' as a FUNC but expected a variable
21 | a = func;
%Error: t/t_func_no_parentheses_bad.v:16:11: Found definition of 'func' as a FUNC but expected a variable
16 | a = func;
| ^~~~
%Error: Exiting due to

7
test_regress/t/t_func_no_parentheses_bad.v
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@ -9,12 +9,7 @@ function static int func();
return ++cnt;
endfunction
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
int a;
initial begin

6
test_regress/t/t_initarray_nonarray.v
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@ -13,11 +13,7 @@ typedef logic [7:0] mask_t [7:0];
parameter mask_t IMP_MASK = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37};
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
mask_t a;
//logic [7:0] a[7:0];

4
test_regress/t/t_inst_array_bad.out
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@ -1,5 +1,5 @@
%Error: t/t_inst_array_bad.v:19:28: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. (IEEE 1800-2023 23.3.3)
%Error: t/t_inst_array_bad.v:14:28: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. (IEEE 1800-2023 23.3.3)
: ... note: In instance 't'
19 | sub sub [7:0] (allbits, onebitbad, bitout);
14 | sub sub [7:0] (allbits, onebitbad, bitout);
| ^~~~~~~~~
%Error: Exiting due to

7
test_regress/t/t_inst_array_bad.v
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@ -4,12 +4,7 @@
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
wire [7:0] bitout;
reg [7:0] allbits;

4
test_regress/t/t_inst_recurse2_bad.out
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@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_inst_recurse2_bad.v:18:8: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped'
%Error-UNSUPPORTED: t/t_inst_recurse2_bad.v:13:8: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped'
: ... note: In instance 't.looped.looped.looped'
18 | module looped ( );
13 | module looped ( );
| ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

7
test_regress/t/t_inst_recurse2_bad.v
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@ -4,12 +4,7 @@
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
looped looped ();

4
test_regress/t/t_inst_recurse_bad.out
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@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_inst_recurse_bad.v:18:8: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): 'looped'
%Error-UNSUPPORTED: t/t_inst_recurse_bad.v:13:8: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): 'looped'
: ... note: self-recursion (module instantiating itself directly) is supported.
18 | module looped ( );
13 | module looped ( );
| ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

7
test_regress/t/t_inst_recurse_bad.v
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@ -4,12 +4,7 @@
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
looped looped ();

4
test_regress/t/t_interface_mismodport_bad.out
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@ -1,5 +1,5 @@
%Error: t/t_interface_mismodport_bad.v:36:12: Can't find definition of 'bad' in dotted signal: 'isub.bad'
36 | isub.bad = i_value;
%Error: t/t_interface_mismodport_bad.v:32:12: Can't find definition of 'bad' in dotted signal: 'isub.bad'
32 | isub.bad = i_value;
| ^~~
... Known scopes under 'bad': <no instances found>
%Error: Exiting due to

6
test_regress/t/t_interface_mismodport_bad.v
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@ -10,12 +10,8 @@ interface ifc;
modport out_modport (output ok);
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
module t (/*AUTOARG*/);
input clk;
integer cyc=1;
ifc itop();

7
test_regress/t/t_interface_parent_scope_bad.v
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@ -17,12 +17,7 @@ module Baz();
Bar bar();
endmodule
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
Baz baz();

8
test_regress/t/t_lint_block_redecl_bad.out
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@ -1,7 +1,7 @@
%Error: t/t_lint_block_redecl_bad.v:21:34: Duplicate declaration of block: 'COMB'
21 | for(i=0; i<9; i++ ) begin: COMB
%Error: t/t_lint_block_redecl_bad.v:17:34: Duplicate declaration of block: 'COMB'
17 | for(i=0; i<9; i++ ) begin: COMB
| ^~~~
t/t_lint_block_redecl_bad.v:18:35: ... Location of original declaration
18 | for(i=0; i<10; i++ ) begin: COMB
t/t_lint_block_redecl_bad.v:14:35: ... Location of original declaration
14 | for(i=0; i<10; i++ ) begin: COMB
| ^~~~
%Error: Exiting due to

6
test_regress/t/t_lint_block_redecl_bad.v
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@ -6,11 +6,7 @@
//bug485, but see t_gen_forif.v for an OK example.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
always_comb begin
integer i;

4
test_regress/t/t_math_countbits_bad.out
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@ -1,5 +1,5 @@
%Error-UNSUPPORTED: t/t_math_countbits_bad.v:14:54: Unsupported: $countbits with more than 3 control fields
14 | assign count = $countbits(32'h123456, '0, '1, 'x, 'z);
%Error-UNSUPPORTED: t/t_math_countbits_bad.v:10:54: Unsupported: $countbits with more than 3 control fields
10 | assign count = $countbits(32'h123456, '0, '1, 'x, 'z);
| ^~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

6
test_regress/t/t_math_countbits_bad.v
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@ -4,11 +4,7 @@
// any use, without warranty, 2020 Yossi Nivin.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
module t(/*AUTOARG*/);
integer count;
assign count = $countbits(32'h123456, '0, '1, 'x, 'z);

7
test_regress/t/t_math_divw.v
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@ -4,12 +4,7 @@
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
// verilator lint_off WIDTH

7
test_regress/t/t_math_sign_extend.v
View File

@ -7,12 +7,7 @@
// without warranty, 2015 by Mike Thyer.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
localparam [ 0:0] one1_lp = 1;
localparam [ 1:0] one2_lp = 1;

8
test_regress/t/t_mod_interface_array3.out
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@ -1,8 +1,8 @@
%Error-UNSUPPORTED: t/t_mod_interface_array3.v:26:20: Unsupported: Multidimensional instances/interfaces.
26 | a_if iface [2:0][1:0];
%Error-UNSUPPORTED: t/t_mod_interface_array3.v:22:20: Unsupported: Multidimensional instances/interfaces.
22 | a_if iface [2:0][1:0];
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_mod_interface_array3.v:28:18: Unsupported: Multidimensional instances/interfaces.
28 | sub i_sub[2:0][1:0] (.s(str));
%Error-UNSUPPORTED: t/t_mod_interface_array3.v:24:18: Unsupported: Multidimensional instances/interfaces.
24 | sub i_sub[2:0][1:0] (.s(str));
| ^
%Error: Exiting due to

6
test_regress/t/t_mod_interface_array3.v
View File

@ -15,11 +15,7 @@ module sub (output string s);
initial s = $sformatf("%m");
endmodule
module t
(
clk
);
input clk;
module t;
string str [2:0][1:0];

7
test_regress/t/t_package_dimport.v
View File

@ -38,10 +38,7 @@ module sub();
endmodule
module t(/*AUTOARG*/
// Inputs
clk
);
module t(/*AUTOARG*/);
import defs::*;
@ -51,8 +48,6 @@ module t(/*AUTOARG*/
localparam MAX_EXPONENT = log2(MAX_COUNT);
localparam EXPONENT_WIDTH = ceil_log2(MAX_EXPONENT + 1);
input clk;
generate
if (WHICH == 1)
begin : which_true

6
test_regress/t/t_package_export.v
View File

@ -50,11 +50,7 @@ package pkg31;
import pkg30::*;
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
reg [pkg11::PARAM1 : 0] bus11;
reg [pkg11::PARAM2 : 0] bus12;

24
test_regress/t/t_package_export_bad.out
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@ -1,28 +1,28 @@
%Error: t/t_package_export.v:45:17: Export object not found: 'pkg1::BAD_DOES_NOT_EXIST'
45 | export pkg1::BAD_DOES_NOT_EXIST;
| ^~~~~~~~~~~~~~~~~~
%Error: t/t_package_export.v:56:16: Can't find definition of scope/variable/func: 'PARAM2'
: ... Suggested alternative: 'PARAM1'
56 | reg [pkg11::PARAM2 : 0] bus12;
| ^~~~~~
%Error: t/t_package_export.v:57:16: Can't find definition of scope/variable/func: 'PARAM3'
: ... Suggested alternative: 'PARAM1'
57 | reg [pkg11::PARAM3 : 0] bus13;
| ^~~~~~
%Error: t/t_package_export.v:60:16: Can't find definition of scope/variable/func: 'PARAM2'
: ... Suggested alternative: 'PARAM1'
60 | reg [pkg11::PARAM2 : 0] bus12;
60 | reg [pkg21::PARAM2 : 0] bus22;
| ^~~~~~
%Error: t/t_package_export.v:61:16: Can't find definition of scope/variable/func: 'PARAM3'
: ... Suggested alternative: 'PARAM1'
61 | reg [pkg11::PARAM3 : 0] bus13;
61 | reg [pkg21::PARAM3 : 0] bus23;
| ^~~~~~
%Error: t/t_package_export.v:64:16: Can't find definition of scope/variable/func: 'PARAM2'
: ... Suggested alternative: 'PARAM1'
64 | reg [pkg21::PARAM2 : 0] bus22;
64 | reg [pkg31::PARAM2 : 0] bus32;
| ^~~~~~
%Error: t/t_package_export.v:65:16: Can't find definition of scope/variable/func: 'PARAM3'
: ... Suggested alternative: 'PARAM1'
65 | reg [pkg21::PARAM3 : 0] bus23;
| ^~~~~~
%Error: t/t_package_export.v:68:16: Can't find definition of scope/variable/func: 'PARAM2'
: ... Suggested alternative: 'PARAM1'
68 | reg [pkg31::PARAM2 : 0] bus32;
| ^~~~~~
%Error: t/t_package_export.v:69:16: Can't find definition of scope/variable/func: 'PARAM3'
: ... Suggested alternative: 'PARAM1'
69 | reg [pkg31::PARAM3 : 0] bus33;
65 | reg [pkg31::PARAM3 : 0] bus33;
| ^~~~~~
%Error: Exiting due to

6
test_regress/t/t_package_twodeep.v
View File

@ -17,11 +17,7 @@ endpackage // pkg1
module t
import pkg1::*; // Test SV 2012 import format
(/*AUTOARG*/
// Inputs
clk
);
input clk;
(/*AUTOARG*/);
reg [PARAM1:0] bus1;

7
test_regress/t/t_packed_concat.v
View File

@ -4,12 +4,7 @@
// without warranty, 2019 by Driss Hafdi
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
typedef logic [15:0] count_t;
typedef bit [31:0] bit_int_t;

12
test_regress/t/t_packed_concat_bad.out
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@ -1,15 +1,15 @@
%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:17:47: Unsized numbers/parameters not allowed in replications.
%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:12:47: Unsized numbers/parameters not allowed in replications.
: ... note: In instance 't'
17 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}};
12 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}};
| ^~~~~
... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest
... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:18:46: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:13:46: Unsized numbers/parameters not allowed in concatenations.
: ... note: In instance 't'
18 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)};
13 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)};
| ^~~~~
%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:18:60: Unsized numbers/parameters not allowed in replications.
%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:13:60: Unsized numbers/parameters not allowed in replications.
: ... note: In instance 't'
18 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)};
13 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)};
| ^
%Error: Exiting due to

7
test_regress/t/t_packed_concat_bad.v
View File

@ -4,12 +4,7 @@
// without warranty, 2019 by Driss Hafdi
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
typedef logic [15:0] count_t;
typedef bit [31:0] bit_int_t;

6
test_regress/t/t_param_public.v
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@ -6,11 +6,7 @@
//bug505
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
parameter TOP_PARAM /*verilator public*/ = 20;

6
test_regress/t/t_param_while.v
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@ -6,11 +6,7 @@
//bug505
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
parameter WIDTH = 33;
localparam MAX_WIDTH = 11;

4
test_regress/t/t_param_width_loc_bad.out
View File

@ -1,6 +1,6 @@
%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:25:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
%Warning-WIDTHTRUNC: t/t_param_width_loc_bad.v:20:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
: ... note: In instance 't.test_i'
25 | parameter logic param = 1'b0
20 | parameter logic param = 1'b0
| ^~~~~
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.

7
test_regress/t/t_param_width_loc_bad.v
View File

@ -4,12 +4,7 @@
// without warranty, 2019 by Driss Hafdi.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
// bug1624
test #(.param(32'd0)) test_i();

6
test_regress/t/t_preproc_kwd.v
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@ -4,11 +4,7 @@
// any use, without warranty, 2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
v95 v95 ();
v01nc v01nc ();

6
test_regress/t/t_select_index2.v
View File

@ -4,11 +4,7 @@
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
reg [7:0] x;
wire [3:0] en;

6
test_regress/t/t_select_little_pack.v
View File

@ -4,11 +4,7 @@
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
// No ascending range warning here
reg [7:0] pack [3:0];

6
test_regress/t/t_stream_integer_type.v
View File

@ -15,11 +15,7 @@
// any use, without warranty, 2020 by Victor Besyakov.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
logic [31:0] packed_data_32;
logic [31:0] packed_data_32_ref;

7
test_regress/t/t_timing_strobe.v
View File

@ -4,11 +4,8 @@
// any use, without warranty, 2022 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
event e1;
event e2;
int v = 0;

7
test_regress/t/t_unpacked_concat.v
View File

@ -4,12 +4,7 @@
// without warranty, 2023 by Yutetsu TAKATSUKASA.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
typedef int AI3[1:3];
AI3 A3;

4
test_regress/t/t_unpacked_concat_bad.out
View File

@ -1,6 +1,6 @@
%Error-UNSUPPORTED: t/t_unpacked_concat_bad.v:17:46: Unsupported: Non-1 replication to form 'bit[31:0]$[1:0]' data type
%Error-UNSUPPORTED: t/t_unpacked_concat_bad.v:12:46: Unsupported: Non-1 replication to form 'bit[31:0]$[1:0]' data type
: ... note: In instance 't'
17 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}};
12 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}};
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

7
test_regress/t/t_unpacked_concat_bad.v
View File

@ -4,12 +4,7 @@
// without warranty, 2019 by Driss Hafdi.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
typedef logic [15:0] count_t;
typedef bit [31:0] bit_int_t;

16
test_regress/t/t_unpacked_concat_bad2.out
View File

@ -1,13 +1,13 @@
%Error: t/t_unpacked_concat_bad2.v:25:15: Array initialization has too many elements. 2 elements are expected, but at least 5 elements exist.
25 | s1 = {s0, s2};
%Error: t/t_unpacked_concat_bad2.v:20:15: Array initialization has too many elements. 2 elements are expected, but at least 5 elements exist.
20 | s1 = {s0, s2};
| ^
%Error: t/t_unpacked_concat_bad2.v:26:23: Array initialization has too many elements. 4 elements are expected, but at least 5 elements exist.
26 | s2 = {s1, s0, s0, s0};
%Error: t/t_unpacked_concat_bad2.v:21:23: Array initialization has too many elements. 4 elements are expected, but at least 5 elements exist.
21 | s2 = {s1, s0, s0, s0};
| ^
%Error: t/t_unpacked_concat_bad2.v:28:17: Item is incompatible with the array type.
28 | s2 = {s0, s3};
%Error: t/t_unpacked_concat_bad2.v:23:17: Item is incompatible with the array type.
23 | s2 = {s0, s3};
| ^~
%Error: t/t_unpacked_concat_bad2.v:30:19: Item is incompatible with the array type.
30 | A9_logic = {A3, 4, 5, A3, 6};
%Error: t/t_unpacked_concat_bad2.v:25:19: Item is incompatible with the array type.
25 | A9_logic = {A3, 4, 5, A3, 6};
| ^~
%Error: Exiting due to

7
test_regress/t/t_unpacked_concat_bad2.v
View File

@ -4,12 +4,7 @@
// without warranty, 2023 by Yutetsu TAKATSUKASA.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
logic [7:0] s0;
logic [7:0] s1[1:2];

6
test_regress/t/t_vams_basic.v
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@ -6,11 +6,7 @@
`begin_keywords "VAMS-2.3"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
module t (/*AUTOARG*/);
task check (integer line, real got, real expec);
real delta;