github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-01 04:07:34 +00:00
Code Issues Packages Projects Releases Wiki Activity

Internals: Misc ANSI port parsing cleanups; baseline for future commit.

Browse Source
This commit is contained in:
Wilson Snyder 2024-12-02 07:21:24 -05:00
parent b4e91c87a6
commit b16b48f458
4 changed files with 24 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/V3Ast.h
View File

@ -904,7 +904,7 @@ public:
TRIWIRE, TRIWIRE,
TRI0, TRI0,
TRI1, TRI1,
PORT, // Used in parser and V3Fork to recognize ports PORT, // Used in parser to recognize ports
BLOCKTEMP, BLOCKTEMP,
MODULETEMP, MODULETEMP,
STMTTEMP, STMTTEMP,

5
src/V3AstNodeOther.h
View File

@ -2082,7 +2082,10 @@ public:
bool isPrimaryIO() const VL_MT_SAFE { return m_primaryIO; } bool isPrimaryIO() const VL_MT_SAFE { return m_primaryIO; }
bool isPrimaryInish() const { return isPrimaryIO() && isNonOutput(); } bool isPrimaryInish() const { return isPrimaryIO() && isNonOutput(); }
bool isIfaceRef() const { return varType() == VVarType::IFACEREF; } bool isIfaceRef() const { return varType() == VVarType::IFACEREF; }
void setIfaceRef() { m_varType = VVarType::IFACEREF; } void setIfaceRef() {
m_direction = VDirection::NONE;
m_varType = VVarType::IFACEREF;
}
bool isIfaceParent() const { return m_isIfaceParent; } bool isIfaceParent() const { return m_isIfaceParent; }
bool isInternal() const { return m_isInternal; } bool isInternal() const { return m_isInternal; }
bool isSignal() const { return varType().isSignal(); } bool isSignal() const { return varType().isSignal(); }

5
src/V3ParseGrammar.cpp
View File

@ -193,7 +193,8 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
AstNodeDType* dtypep = GRAMMARP->m_varDTypep; AstNodeDType* dtypep = GRAMMARP->m_varDTypep;
UINFO(5, " creVar " << name << " decl=" << GRAMMARP->m_varDecl << " io=" UINFO(5, " creVar " << name << " decl=" << GRAMMARP->m_varDecl << " io="
<< GRAMMARP->m_varIO << " dt=" << (dtypep ? "set" : "") << endl); << GRAMMARP->m_varIO << " dt=" << (dtypep ? "set" : "") << endl);
if (GRAMMARP->m_varIO == VDirection::NONE && GRAMMARP->m_varDecl == VVarType::PORT) { if (GRAMMARP->m_varIO == VDirection::NONE // In non-ANSI port list
&& GRAMMARP->m_varDecl == VVarType::PORT) {
// Just a port list with variable name (not v2k format); AstPort already created // Just a port list with variable name (not v2k format); AstPort already created
if (dtypep) fileline->v3warn(E_UNSUPPORTED, "Unsupported: Ranges ignored in port-lists"); if (dtypep) fileline->v3warn(E_UNSUPPORTED, "Unsupported: Ranges ignored in port-lists");
if (arrayp) VL_DO_DANGLING(arrayp->deleteTree(), arrayp); if (arrayp) VL_DO_DANGLING(arrayp->deleteTree(), arrayp);
@ -222,7 +223,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
// UINFO(0,"CREVAR "<<fileline->ascii()<<" decl="<<GRAMMARP->m_varDecl.ascii()<<" // UINFO(0,"CREVAR "<<fileline->ascii()<<" decl="<<GRAMMARP->m_varDecl.ascii()<<"
// io="<<GRAMMARP->m_varIO.ascii()<<endl); // io="<<GRAMMARP->m_varIO.ascii()<<endl);
VVarType type = GRAMMARP->m_varDecl; VVarType type = GRAMMARP->m_varDecl;
if (type == VVarType::UNKNOWN) { if (type == VVarType::UNKNOWN) { // e.g. "output" non-ANSI standalone direction (vs "reg")
if (GRAMMARP->m_varIO.isAny()) { if (GRAMMARP->m_varIO.isAny()) {
type = VVarType::PORT; type = VVarType::PORT;
} else { } else {

27
src/verilog.y
View File

@ -323,6 +323,11 @@ int V3ParseGrammar::s_modTypeImpNum = 0;
{ GRAMMARP->m_varDecl = VVarType::type; } { GRAMMARP->m_varDecl = VVarType::type; }
#define VARIO(type) \ #define VARIO(type) \
{ GRAMMARP->m_varIO = VDirection::type; } { GRAMMARP->m_varIO = VDirection::type; }
// Set direction to default-input when detect inside an ANSI port list
#define VARIOANSI(type) \
{ \
if (GRAMMARP->m_varIO == VDirection::NONE) VARIO(INPUT); \
}
#define VARLIFE(flag) \ #define VARLIFE(flag) \
{ GRAMMARP->m_varLifetime = flag; } { GRAMMARP->m_varLifetime = flag; }
#define VARDTYPE(dtypep) \ #define VARDTYPE(dtypep) \
@ -1471,7 +1476,7 @@ portsStarE<nodep>: // IEEE: .* + list_of_ports + list_of_port_decla
{ $$ = $3; VARRESET_NONLIST(UNKNOWN); GRAMMARP->m_pinAnsi = false; } { $$ = $3; VARRESET_NONLIST(UNKNOWN); GRAMMARP->m_pinAnsi = false; }
; ;
list_of_portsE<nodep>: // IEEE: list_of_ports + list_of_port_declarations list_of_portsE<nodep>: // IEEE: [ list_of_ports + list_of_port_declarations ]
portAndTagE { $$ = $1; } portAndTagE { $$ = $1; }
| list_of_portsE ',' portAndTagE { $$ = addNextNull($1, $3); } | list_of_portsE ',' portAndTagE { $$ = addNextNull($1, $3); }
; ;
@ -1519,13 +1524,13 @@ port<nodep>: // ==IEEE: port
{ // VAR for now, but V3LinkCells may call setIfcaeRef on it later { // VAR for now, but V3LinkCells may call setIfcaeRef on it later
$$ = $3; VARDECL(VAR); VARIO(NONE); $$ = $3; VARDECL(VAR); VARIO(NONE);
AstNodeDType* const dtp = new AstIfaceRefDType{$<fl>2, "", *$2}; AstNodeDType* const dtp = new AstIfaceRefDType{$<fl>2, "", *$2};
VARDTYPE(dtp); VARDTYPE(dtp); VARIOANSI();
addNextNull($$, VARDONEP($$, $4, $5)); } addNextNull($$, VARDONEP($$, $4, $5)); }
| portDirNetE id/*interface*/ '.' idAny/*modport*/ portSig variable_dimensionListE sigAttrListE | portDirNetE id/*interface*/ '.' idAny/*modport*/ portSig variable_dimensionListE sigAttrListE
{ // VAR for now, but V3LinkCells may call setIfcaeRef on it later { // VAR for now, but V3LinkCells may call setIfcaeRef on it later
$$ = $5; VARDECL(VAR); VARIO(NONE); $$ = $5; VARDECL(VAR); VARIO(NONE);
AstNodeDType* const dtp = new AstIfaceRefDType{$<fl>2, $<fl>4, "", *$2, *$4}; AstNodeDType* const dtp = new AstIfaceRefDType{$<fl>2, $<fl>4, "", *$2, *$4};
VARDTYPE(dtp); VARDTYPE(dtp); VARIOANSI();
addNextNull($$, VARDONEP($$, $6, $7)); } addNextNull($$, VARDONEP($$, $6, $7)); }
| portDirNetE yINTERFACE portSig rangeListE sigAttrListE | portDirNetE yINTERFACE portSig rangeListE sigAttrListE
{ $$ = nullptr; BBUNSUP($<fl>2, "Unsupported: generic interfaces"); } { $$ = nullptr; BBUNSUP($<fl>2, "Unsupported: generic interfaces"); }
@ -1537,7 +1542,7 @@ port<nodep>: // ==IEEE: port
BBUNSUP($<fl>2, "Unsupported: interconnect"); BBUNSUP($<fl>2, "Unsupported: interconnect");
AstNodeDType* const dtp = GRAMMARP->addRange( AstNodeDType* const dtp = GRAMMARP->addRange(
new AstBasicDType{$2, LOGIC_IMPLICIT, $3}, $4, true); new AstBasicDType{$2, LOGIC_IMPLICIT, $3}, $4, true);
VARDTYPE(dtp); VARDTYPE(dtp); VARIOANSI();
addNextNull($$, VARDONEP($$, $6, $7)); } addNextNull($$, VARDONEP($$, $6, $7)); }
// //
// // IEEE: ansi_port_declaration, with [port_direction] removed // // IEEE: ansi_port_declaration, with [port_direction] removed
@ -1576,15 +1581,15 @@ port<nodep>: // ==IEEE: port
// // IEEE: portDirNetE data_type '.' portSig -> handled with AstDot in expr. // // IEEE: portDirNetE data_type '.' portSig -> handled with AstDot in expr.
// //
| portDirNetE data_type portSig variable_dimensionListE sigAttrListE | portDirNetE data_type portSig variable_dimensionListE sigAttrListE
{ $$ = $3; VARDTYPE($2); addNextNull($$, VARDONEP($$, $4, $5)); } { $$ = $3; VARDTYPE($2); VARIOANSI(); addNextNull($$, VARDONEP($$, $4, $5)); }
| portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE | portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE
{ $$ = $4; VARDTYPE($3); addNextNull($$, VARDONEP($$, $5, $6)); } { $$ = $4; VARDTYPE($3); VARIOANSI(); addNextNull($$, VARDONEP($$, $5, $6)); }
| portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE | portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE
{ $$ = $4; VARDTYPE($3); addNextNull($$, VARDONEP($$, $5, $6)); } { $$ = $4; VARDTYPE($3); VARIOANSI(); addNextNull($$, VARDONEP($$, $5, $6)); }
| portDirNetE signing portSig variable_dimensionListE sigAttrListE | portDirNetE signing portSig variable_dimensionListE sigAttrListE
{ $$ = $3; { $$ = $3;
AstNodeDType* const dtp = new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2}; AstNodeDType* const dtp = new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2};
VARDTYPE_NDECL(dtp); VARDTYPE_NDECL(dtp); VARIOANSI();
addNextNull($$, VARDONEP($$, $4, $5)); } addNextNull($$, VARDONEP($$, $4, $5)); }
| portDirNetE signingE rangeList portSig variable_dimensionListE sigAttrListE | portDirNetE signingE rangeList portSig variable_dimensionListE sigAttrListE
{ $$ = $4; { $$ = $4;
@ -1596,13 +1601,13 @@ port<nodep>: // ==IEEE: port
{ $$ = $2; /*VARDTYPE-same*/ addNextNull($$, VARDONEP($$, $3, $4)); } { $$ = $2; /*VARDTYPE-same*/ addNextNull($$, VARDONEP($$, $3, $4)); }
// //
| portDirNetE data_type portSig variable_dimensionListE sigAttrListE '=' constExpr | portDirNetE data_type portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $3; VARDTYPE($2); { $$ = $3; VARDTYPE($2); VARIOANSI();
if (AstVar* vp = VARDONEP($$, $4, $5)) { addNextNull($$, vp); vp->valuep($7); } } if (AstVar* vp = VARDONEP($$, $4, $5)) { addNextNull($$, vp); vp->valuep($7); } }
| portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE '=' constExpr | portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $4; VARDTYPE($3); { $$ = $4; VARDTYPE($3); VARIOANSI();
if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } } if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
| portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE '=' constExpr | portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $4; VARDTYPE($3); { $$ = $4; VARDTYPE($3); VARIOANSI();
if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } } if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
| portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE '=' constExpr | portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE '=' constExpr
{ $$ = $2; /*VARDTYPE-same*/ { $$ = $2; /*VARDTYPE-same*/