From b16b48f45812cd51aea89ad508899cbffda0d7d0 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 2 Dec 2024 07:21:24 -0500 Subject: [PATCH] Internals: Misc ANSI port parsing cleanups; baseline for future commit. --- src/V3Ast.h | 2 +- src/V3AstNodeOther.h | 5 ++++- src/V3ParseGrammar.cpp | 5 +++-- src/verilog.y | 27 ++++++++++++++++----------- 4 files changed, 24 insertions(+), 15 deletions(-) diff --git a/src/V3Ast.h b/src/V3Ast.h index cbee6890a..961dd146c 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -904,7 +904,7 @@ public: TRIWIRE, TRI0, TRI1, - PORT, // Used in parser and V3Fork to recognize ports + PORT, // Used in parser to recognize ports BLOCKTEMP, MODULETEMP, STMTTEMP, diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 155237d80..ec8c777e3 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -2082,7 +2082,10 @@ public: bool isPrimaryIO() const VL_MT_SAFE { return m_primaryIO; } bool isPrimaryInish() const { return isPrimaryIO() && isNonOutput(); } bool isIfaceRef() const { return varType() == VVarType::IFACEREF; } - void setIfaceRef() { m_varType = VVarType::IFACEREF; } + void setIfaceRef() { + m_direction = VDirection::NONE; + m_varType = VVarType::IFACEREF; + } bool isIfaceParent() const { return m_isIfaceParent; } bool isInternal() const { return m_isInternal; } bool isSignal() const { return varType().isSignal(); } diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp index 6451ba514..481965f22 100644 --- a/src/V3ParseGrammar.cpp +++ b/src/V3ParseGrammar.cpp @@ -193,7 +193,8 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name, AstNodeDType* dtypep = GRAMMARP->m_varDTypep; UINFO(5, " creVar " << name << " decl=" << GRAMMARP->m_varDecl << " io=" << GRAMMARP->m_varIO << " dt=" << (dtypep ? "set" : "") << endl); - if (GRAMMARP->m_varIO == VDirection::NONE && GRAMMARP->m_varDecl == VVarType::PORT) { + if (GRAMMARP->m_varIO == VDirection::NONE // In non-ANSI port list + && GRAMMARP->m_varDecl == VVarType::PORT) { // Just a port list with variable name (not v2k format); AstPort already created if (dtypep) fileline->v3warn(E_UNSUPPORTED, "Unsupported: Ranges ignored in port-lists"); if (arrayp) VL_DO_DANGLING(arrayp->deleteTree(), arrayp); @@ -222,7 +223,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name, // UINFO(0,"CREVAR "<ascii()<<" decl="<m_varDecl.ascii()<<" // io="<m_varIO.ascii()<m_varDecl; - if (type == VVarType::UNKNOWN) { + if (type == VVarType::UNKNOWN) { // e.g. "output" non-ANSI standalone direction (vs "reg") if (GRAMMARP->m_varIO.isAny()) { type = VVarType::PORT; } else { diff --git a/src/verilog.y b/src/verilog.y index c04d47612..9afdbfbdc 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -323,6 +323,11 @@ int V3ParseGrammar::s_modTypeImpNum = 0; { GRAMMARP->m_varDecl = VVarType::type; } #define VARIO(type) \ { GRAMMARP->m_varIO = VDirection::type; } +// Set direction to default-input when detect inside an ANSI port list +#define VARIOANSI(type) \ + { \ + if (GRAMMARP->m_varIO == VDirection::NONE) VARIO(INPUT); \ + } #define VARLIFE(flag) \ { GRAMMARP->m_varLifetime = flag; } #define VARDTYPE(dtypep) \ @@ -1471,7 +1476,7 @@ portsStarE: // IEEE: .* + list_of_ports + list_of_port_decla { $$ = $3; VARRESET_NONLIST(UNKNOWN); GRAMMARP->m_pinAnsi = false; } ; -list_of_portsE: // IEEE: list_of_ports + list_of_port_declarations +list_of_portsE: // IEEE: [ list_of_ports + list_of_port_declarations ] portAndTagE { $$ = $1; } | list_of_portsE ',' portAndTagE { $$ = addNextNull($1, $3); } ; @@ -1519,13 +1524,13 @@ port: // ==IEEE: port { // VAR for now, but V3LinkCells may call setIfcaeRef on it later $$ = $3; VARDECL(VAR); VARIO(NONE); AstNodeDType* const dtp = new AstIfaceRefDType{$2, "", *$2}; - VARDTYPE(dtp); + VARDTYPE(dtp); VARIOANSI(); addNextNull($$, VARDONEP($$, $4, $5)); } | portDirNetE id/*interface*/ '.' idAny/*modport*/ portSig variable_dimensionListE sigAttrListE { // VAR for now, but V3LinkCells may call setIfcaeRef on it later $$ = $5; VARDECL(VAR); VARIO(NONE); AstNodeDType* const dtp = new AstIfaceRefDType{$2, $4, "", *$2, *$4}; - VARDTYPE(dtp); + VARDTYPE(dtp); VARIOANSI(); addNextNull($$, VARDONEP($$, $6, $7)); } | portDirNetE yINTERFACE portSig rangeListE sigAttrListE { $$ = nullptr; BBUNSUP($2, "Unsupported: generic interfaces"); } @@ -1537,7 +1542,7 @@ port: // ==IEEE: port BBUNSUP($2, "Unsupported: interconnect"); AstNodeDType* const dtp = GRAMMARP->addRange( new AstBasicDType{$2, LOGIC_IMPLICIT, $3}, $4, true); - VARDTYPE(dtp); + VARDTYPE(dtp); VARIOANSI(); addNextNull($$, VARDONEP($$, $6, $7)); } // // // IEEE: ansi_port_declaration, with [port_direction] removed @@ -1576,15 +1581,15 @@ port: // ==IEEE: port // // IEEE: portDirNetE data_type '.' portSig -> handled with AstDot in expr. // | portDirNetE data_type portSig variable_dimensionListE sigAttrListE - { $$ = $3; VARDTYPE($2); addNextNull($$, VARDONEP($$, $4, $5)); } + { $$ = $3; VARDTYPE($2); VARIOANSI(); addNextNull($$, VARDONEP($$, $4, $5)); } | portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE - { $$ = $4; VARDTYPE($3); addNextNull($$, VARDONEP($$, $5, $6)); } + { $$ = $4; VARDTYPE($3); VARIOANSI(); addNextNull($$, VARDONEP($$, $5, $6)); } | portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE - { $$ = $4; VARDTYPE($3); addNextNull($$, VARDONEP($$, $5, $6)); } + { $$ = $4; VARDTYPE($3); VARIOANSI(); addNextNull($$, VARDONEP($$, $5, $6)); } | portDirNetE signing portSig variable_dimensionListE sigAttrListE { $$ = $3; AstNodeDType* const dtp = new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2}; - VARDTYPE_NDECL(dtp); + VARDTYPE_NDECL(dtp); VARIOANSI(); addNextNull($$, VARDONEP($$, $4, $5)); } | portDirNetE signingE rangeList portSig variable_dimensionListE sigAttrListE { $$ = $4; @@ -1596,13 +1601,13 @@ port: // ==IEEE: port { $$ = $2; /*VARDTYPE-same*/ addNextNull($$, VARDONEP($$, $3, $4)); } // | portDirNetE data_type portSig variable_dimensionListE sigAttrListE '=' constExpr - { $$ = $3; VARDTYPE($2); + { $$ = $3; VARDTYPE($2); VARIOANSI(); if (AstVar* vp = VARDONEP($$, $4, $5)) { addNextNull($$, vp); vp->valuep($7); } } | portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE '=' constExpr - { $$ = $4; VARDTYPE($3); + { $$ = $4; VARDTYPE($3); VARIOANSI(); if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } } | portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE '=' constExpr - { $$ = $4; VARDTYPE($3); + { $$ = $4; VARDTYPE($3); VARIOANSI(); if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } } | portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE '=' constExpr { $$ = $2; /*VARDTYPE-same*/