Tests: Add t_interface_find

test_regress/t/t_interface_find.py

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+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()

test_regress/t/t_interface_find.v

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+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2013 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// Auto-resolved by t_interface_find_ifc.v
+// interface t_interface_find_ifc;
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc=1;
+
+   t_interface_find_ifc itop();
+
+   sub  c1 (.isub(itop),
+            .i_value(4'h4));
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==20) begin
+         if (c1.i_value != 4) $stop;  // 'Normal' crossref just for comparison
+         if (itop.value != 4) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
+
+module sub
+  (
+   t_interface_find_ifc isub,
+   input logic [3:0] i_value
+   );
+
+   always @* begin
+      isub.value = i_value;
+   end
+endmodule : sub

test_regress/t/t_interface_find_ifc.v

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+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2013 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface t_interface_find_ifc;
+   logic [3:0] value;
+endinterface