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Internals: Misc ANSI port parsing cleanups; baseline for future commit.
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@ -904,7 +904,7 @@ public:
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TRIWIRE,
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TRI0,
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TRI1,
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PORT, // Used in parser and V3Fork to recognize ports
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PORT, // Used in parser to recognize ports
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BLOCKTEMP,
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MODULETEMP,
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STMTTEMP,
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@ -2082,7 +2082,10 @@ public:
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bool isPrimaryIO() const VL_MT_SAFE { return m_primaryIO; }
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bool isPrimaryInish() const { return isPrimaryIO() && isNonOutput(); }
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bool isIfaceRef() const { return varType() == VVarType::IFACEREF; }
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void setIfaceRef() { m_varType = VVarType::IFACEREF; }
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void setIfaceRef() {
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m_direction = VDirection::NONE;
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m_varType = VVarType::IFACEREF;
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}
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bool isIfaceParent() const { return m_isIfaceParent; }
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bool isInternal() const { return m_isInternal; }
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bool isSignal() const { return varType().isSignal(); }
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@ -193,7 +193,8 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
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AstNodeDType* dtypep = GRAMMARP->m_varDTypep;
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UINFO(5, " creVar " << name << " decl=" << GRAMMARP->m_varDecl << " io="
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<< GRAMMARP->m_varIO << " dt=" << (dtypep ? "set" : "") << endl);
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if (GRAMMARP->m_varIO == VDirection::NONE && GRAMMARP->m_varDecl == VVarType::PORT) {
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if (GRAMMARP->m_varIO == VDirection::NONE // In non-ANSI port list
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&& GRAMMARP->m_varDecl == VVarType::PORT) {
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// Just a port list with variable name (not v2k format); AstPort already created
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if (dtypep) fileline->v3warn(E_UNSUPPORTED, "Unsupported: Ranges ignored in port-lists");
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if (arrayp) VL_DO_DANGLING(arrayp->deleteTree(), arrayp);
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@ -222,7 +223,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
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// UINFO(0,"CREVAR "<<fileline->ascii()<<" decl="<<GRAMMARP->m_varDecl.ascii()<<"
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// io="<<GRAMMARP->m_varIO.ascii()<<endl);
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VVarType type = GRAMMARP->m_varDecl;
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if (type == VVarType::UNKNOWN) {
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if (type == VVarType::UNKNOWN) { // e.g. "output" non-ANSI standalone direction (vs "reg")
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if (GRAMMARP->m_varIO.isAny()) {
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type = VVarType::PORT;
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} else {
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@ -323,6 +323,11 @@ int V3ParseGrammar::s_modTypeImpNum = 0;
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{ GRAMMARP->m_varDecl = VVarType::type; }
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#define VARIO(type) \
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{ GRAMMARP->m_varIO = VDirection::type; }
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// Set direction to default-input when detect inside an ANSI port list
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#define VARIOANSI(type) \
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{ \
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if (GRAMMARP->m_varIO == VDirection::NONE) VARIO(INPUT); \
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}
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#define VARLIFE(flag) \
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{ GRAMMARP->m_varLifetime = flag; }
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#define VARDTYPE(dtypep) \
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@ -1471,7 +1476,7 @@ portsStarE<nodep>: // IEEE: .* + list_of_ports + list_of_port_decla
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{ $$ = $3; VARRESET_NONLIST(UNKNOWN); GRAMMARP->m_pinAnsi = false; }
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;
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list_of_portsE<nodep>: // IEEE: list_of_ports + list_of_port_declarations
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list_of_portsE<nodep>: // IEEE: [ list_of_ports + list_of_port_declarations ]
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portAndTagE { $$ = $1; }
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| list_of_portsE ',' portAndTagE { $$ = addNextNull($1, $3); }
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;
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@ -1519,13 +1524,13 @@ port<nodep>: // ==IEEE: port
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{ // VAR for now, but V3LinkCells may call setIfcaeRef on it later
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$$ = $3; VARDECL(VAR); VARIO(NONE);
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AstNodeDType* const dtp = new AstIfaceRefDType{$<fl>2, "", *$2};
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VARDTYPE(dtp);
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VARDTYPE(dtp); VARIOANSI();
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addNextNull($$, VARDONEP($$, $4, $5)); }
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| portDirNetE id/*interface*/ '.' idAny/*modport*/ portSig variable_dimensionListE sigAttrListE
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{ // VAR for now, but V3LinkCells may call setIfcaeRef on it later
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$$ = $5; VARDECL(VAR); VARIO(NONE);
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AstNodeDType* const dtp = new AstIfaceRefDType{$<fl>2, $<fl>4, "", *$2, *$4};
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VARDTYPE(dtp);
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VARDTYPE(dtp); VARIOANSI();
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addNextNull($$, VARDONEP($$, $6, $7)); }
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| portDirNetE yINTERFACE portSig rangeListE sigAttrListE
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{ $$ = nullptr; BBUNSUP($<fl>2, "Unsupported: generic interfaces"); }
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@ -1537,7 +1542,7 @@ port<nodep>: // ==IEEE: port
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BBUNSUP($<fl>2, "Unsupported: interconnect");
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AstNodeDType* const dtp = GRAMMARP->addRange(
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new AstBasicDType{$2, LOGIC_IMPLICIT, $3}, $4, true);
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VARDTYPE(dtp);
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VARDTYPE(dtp); VARIOANSI();
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addNextNull($$, VARDONEP($$, $6, $7)); }
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//
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// // IEEE: ansi_port_declaration, with [port_direction] removed
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@ -1576,15 +1581,15 @@ port<nodep>: // ==IEEE: port
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// // IEEE: portDirNetE data_type '.' portSig -> handled with AstDot in expr.
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//
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| portDirNetE data_type portSig variable_dimensionListE sigAttrListE
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{ $$ = $3; VARDTYPE($2); addNextNull($$, VARDONEP($$, $4, $5)); }
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{ $$ = $3; VARDTYPE($2); VARIOANSI(); addNextNull($$, VARDONEP($$, $4, $5)); }
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| portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE
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{ $$ = $4; VARDTYPE($3); addNextNull($$, VARDONEP($$, $5, $6)); }
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{ $$ = $4; VARDTYPE($3); VARIOANSI(); addNextNull($$, VARDONEP($$, $5, $6)); }
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| portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE
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{ $$ = $4; VARDTYPE($3); addNextNull($$, VARDONEP($$, $5, $6)); }
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{ $$ = $4; VARDTYPE($3); VARIOANSI(); addNextNull($$, VARDONEP($$, $5, $6)); }
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| portDirNetE signing portSig variable_dimensionListE sigAttrListE
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{ $$ = $3;
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AstNodeDType* const dtp = new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2};
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VARDTYPE_NDECL(dtp);
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VARDTYPE_NDECL(dtp); VARIOANSI();
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addNextNull($$, VARDONEP($$, $4, $5)); }
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| portDirNetE signingE rangeList portSig variable_dimensionListE sigAttrListE
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{ $$ = $4;
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@ -1596,13 +1601,13 @@ port<nodep>: // ==IEEE: port
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{ $$ = $2; /*VARDTYPE-same*/ addNextNull($$, VARDONEP($$, $3, $4)); }
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//
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| portDirNetE data_type portSig variable_dimensionListE sigAttrListE '=' constExpr
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{ $$ = $3; VARDTYPE($2);
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{ $$ = $3; VARDTYPE($2); VARIOANSI();
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if (AstVar* vp = VARDONEP($$, $4, $5)) { addNextNull($$, vp); vp->valuep($7); } }
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| portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE '=' constExpr
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{ $$ = $4; VARDTYPE($3);
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{ $$ = $4; VARDTYPE($3); VARIOANSI();
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if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
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| portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE '=' constExpr
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{ $$ = $4; VARDTYPE($3);
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{ $$ = $4; VARDTYPE($3); VARIOANSI();
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if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
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| portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE '=' constExpr
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{ $$ = $2; /*VARDTYPE-same*/
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